X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Ffpadd%2Fadd1.py;fp=src%2Fieee754%2Ffpadd%2Fadd1.py;h=4b92ad1ad28c769285e3c08ab972cd8f8679ef0b;hb=f202152c8467afc84e9377b5e8f224eb8a9784e6;hp=9004be8f57b3d6058ca13094dda3c0d61e31cff5;hpb=5104d9bfc2df4104193a1e9e5930630242f11bf0;p=ieee754fpu.git

diff --git a/src/ieee754/fpadd/add1.py b/src/ieee754/fpadd/add1.py
index 9004be8f..4b92ad1a 100644
--- a/src/ieee754/fpadd/add1.py
+++ b/src/ieee754/fpadd/add1.py
@@ -8,12 +8,12 @@ from nmigen import Module, Signal
 from nmigen.cli import main, verilog
 from math import log
 
-from nmutil.pipemodbase import FPModBase
+from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.postcalc import FPAddStage1Data
 from ieee754.fpadd.add0 import FPAddStage0Data
 
 
-class FPAddStage1Mod(FPModBase):
+class FPAddStage1Mod(PipeModBase):
     """ Second stage of add: preparation for normalisation.
         detects when tot sum is too big (tot[27] is kinda a carry bit)
     """