X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Ffpadd%2Fstatemachine.py;fp=src%2Fieee754%2Ffpadd%2Fstatemachine.py;h=918e35a2d81ff4a6d9220918b7fec8ef998208ce;hb=2387f838fe6928dc8a60ffbc85d4197579433fc0;hp=4c1365441b0c509c1b8ee07521f5c608f014ee6a;hpb=1bf29821ee5143ef8ba51e3dc0a92002c8a9d3e0;p=ieee754fpu.git

diff --git a/src/ieee754/fpadd/statemachine.py b/src/ieee754/fpadd/statemachine.py
index 4c136544..918e35a2 100644
--- a/src/ieee754/fpadd/statemachine.py
+++ b/src/ieee754/fpadd/statemachine.py
@@ -2,7 +2,7 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Cat, Mux, Array, Const
+from nmigen import Module, Signal, Cat, Mux, Array, Const, Elaboratable
 from nmigen.cli import main, verilog
 from math import log
 
@@ -46,7 +46,7 @@ class FPOpData:
         return list(self)
 
 
-class FPADDBaseMod:
+class FPADDBaseMod(Elaboratable):
 
     def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
         """ IEEE754 FP Add
@@ -268,7 +268,7 @@ class FPADDBase(FPState):
                 m.d.sync += self.out_z.stb.eq(1)
 
 
-class FPADD(FPID):
+class FPADD(FPID, Elaboratable):
     """ FPADD: stages as follows:
 
         FPGetOp (a)