X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Ffpdiv%2Fpipeline.py;fp=src%2Fieee754%2Ffpdiv%2Fpipeline.py;h=4330df44525807d38fac114b462a035bd5f6996c;hb=fe190770cd763589e34d98683fd9723fd535e483;hp=bcd99e26dddcffbf35aa6cfe75511312149022d8;hpb=eb58938610455da3a0c9ae4bf85bd168e06cf17b;p=ieee754fpu.git

diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index bcd99e26..4330df44 100644
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -156,7 +156,7 @@ class FPDIVMuxInOut(ReservationStations):
     """
 
     def __init__(self, width, num_rows, op_wid=2):
-        self.id_wid = num_bits(width)  # FIXME: shouldn't this be num_rows?
+        self.id_wid = num_bits(num_rows)
         self.pspec = PipelineSpec(width, self.id_wid, op_wid)
         # get the standard mantissa width, store in the pspec
         fmt = FPFormat.standard(width)