X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Fpart_mul_add%2Fadder.py;fp=src%2Fieee754%2Fpart_mul_add%2Fadder.py;h=2e504368c1c664a3b51b553338ca4231d0431d3b;hb=0acaedc92d1697bfe61b2834aea6332b5b095b77;hp=c2e75257340702050943d948774a4085e391072a;hpb=8c4baccb7201d450840015f27f05ff53095e6c82;p=ieee754fpu.git

diff --git a/src/ieee754/part_mul_add/adder.py b/src/ieee754/part_mul_add/adder.py
index c2e75257..2e504368 100644
--- a/src/ieee754/part_mul_add/adder.py
+++ b/src/ieee754/part_mul_add/adder.py
@@ -204,7 +204,7 @@ class PartitionedAdder(Elaboratable):
             pi = i/self.pmul # double the range of the partition point test
             if pi.is_integer() and pi in self.part_pts:
                 # add extra bit set to 0 + 0 for enabled partition points
-                a_bit = Signal()
+                a_bit = Signal(name="a_bit_%d" % i, reset_less=True)
                 carry_in = self.carry_in[carry_bit] # convenience
                 m.d.comb += a_bit.eq(self.part_pts[pi].implies(carry_in))
                 # and 1 + 0 for disabled partition points