X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Fpart_mul_add%2Fadder.py;fp=src%2Fieee754%2Fpart_mul_add%2Fadder.py;h=e07101ad851a2e00b79d043b873217e6a74b9e0f;hb=87043a84ae08849e855490d62ae8c948c7826633;hp=84d8d9108c6ddce8c31c2a92db6ec7f9a109d372;hpb=285be838f380791699f878cf4b9b2d6161c4f507;p=ieee754fpu.git

diff --git a/src/ieee754/part_mul_add/adder.py b/src/ieee754/part_mul_add/adder.py
index 84d8d910..e07101ad 100644
--- a/src/ieee754/part_mul_add/adder.py
+++ b/src/ieee754/part_mul_add/adder.py
@@ -199,7 +199,8 @@ class PartitionedAdder(Elaboratable):
                 ea.append(expanded_a[expanded_index])
                 al.append(a_bit) # add extra bit in a
                 eb.append(expanded_b[expanded_index])
-                bl.append(self.carry_in[carry_bit]) # yes, add a zero
+                bl.append(self.carry_in[carry_bit] &
+                          self.partition_points[pi]) # yes, add a zero
                 co.append(expanded_o[expanded_index])
                 cl.append(self.carry_out[carry_bit-1])
                 expanded_index += 1 # skip the extra point.  NOT in the output