X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fintel%2Fblorp%2Fblorp_clear.c;h=d7668eac3ca99888e9a422dbeea8e6e82635edd3;hb=5e43a75950e8562e65cb2d1d1f07781300a29d4f;hp=369e18726f2aeea2c9ab7682ac99a815ba0adc67;hpb=b46a07175823ec476505cb8a0f8c353e5183d748;p=mesa.git diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c index 369e18726f2..d7668eac3ca 100644 --- a/src/intel/blorp/blorp_clear.c +++ b/src/intel/blorp/blorp_clear.c @@ -25,11 +25,12 @@ #include "main/macros.h" /* Needed for MAX3 and MAX2 for format_rgb9e5 */ #include "util/format_rgb9e5.h" +#include "util/format_srgb.h" #include "blorp_priv.h" #include "compiler/brw_eu_defines.h" -#include "compiler/nir/nir_builder.h" +#include "blorp_nir_builder.h" #define FILE_DEBUG_FLAG DEBUG_BLORP @@ -37,51 +38,74 @@ struct brw_blorp_const_color_prog_key { enum blorp_shader_type shader_type; /* Must be BLORP_SHADER_TYPE_CLEAR */ bool use_simd16_replicated_data; + bool clear_rgb_as_red; bool pad[3]; }; static bool -blorp_params_get_clear_kernel(struct blorp_context *blorp, +blorp_params_get_clear_kernel(struct blorp_batch *batch, struct blorp_params *params, - bool use_replicated_data) + bool use_replicated_data, + bool clear_rgb_as_red) { + struct blorp_context *blorp = batch->blorp; + const struct brw_blorp_const_color_prog_key blorp_key = { .shader_type = BLORP_SHADER_TYPE_CLEAR, .use_simd16_replicated_data = use_replicated_data, + .clear_rgb_as_red = clear_rgb_as_red, }; - if (blorp->lookup_shader(blorp, &blorp_key, sizeof(blorp_key), + if (blorp->lookup_shader(batch, &blorp_key, sizeof(blorp_key), ¶ms->wm_prog_kernel, ¶ms->wm_prog_data)) return true; void *mem_ctx = ralloc_context(NULL); nir_builder b; - nir_builder_init_simple_shader(&b, mem_ctx, MESA_SHADER_FRAGMENT, NULL); - b.shader->info.name = ralloc_strdup(b.shader, "BLORP-clear"); + blorp_nir_init_shader(&b, mem_ctx, MESA_SHADER_FRAGMENT, "BLORP-clear"); nir_variable *v_color = BLORP_CREATE_NIR_INPUT(b.shader, clear_color, glsl_vec4_type()); + nir_ssa_def *color = nir_load_var(&b, v_color); + + if (clear_rgb_as_red) { + nir_variable *frag_coord = + nir_variable_create(b.shader, nir_var_shader_in, + glsl_vec4_type(), "gl_FragCoord"); + frag_coord->data.location = VARYING_SLOT_POS; + + nir_ssa_def *pos = nir_f2i32(&b, nir_load_var(&b, frag_coord)); + nir_ssa_def *comp = nir_umod(&b, nir_channel(&b, pos, 0), + nir_imm_int(&b, 3)); + nir_ssa_def *color_component = + nir_bcsel(&b, nir_ieq(&b, comp, nir_imm_int(&b, 0)), + nir_channel(&b, color, 0), + nir_bcsel(&b, nir_ieq(&b, comp, nir_imm_int(&b, 1)), + nir_channel(&b, color, 1), + nir_channel(&b, color, 2))); + + nir_ssa_def *u = nir_ssa_undef(&b, 1, 32); + color = nir_vec4(&b, color_component, u, u, u); + } nir_variable *frag_color = nir_variable_create(b.shader, nir_var_shader_out, glsl_vec4_type(), "gl_FragColor"); frag_color->data.location = FRAG_RESULT_COLOR; - - nir_copy_var(&b, frag_color, v_color); + nir_store_var(&b, frag_color, color, 0xf); struct brw_wm_prog_key wm_key; brw_blorp_init_wm_prog_key(&wm_key); struct brw_wm_prog_data prog_data; - unsigned program_size; const unsigned *program = blorp_compile_fs(blorp, mem_ctx, b.shader, &wm_key, use_replicated_data, - &prog_data, &program_size); + &prog_data); bool result = - blorp->upload_shader(blorp, &blorp_key, sizeof(blorp_key), - program, program_size, + blorp->upload_shader(batch, &blorp_key, sizeof(blorp_key), + program, prog_data.base.program_size, &prog_data.base, sizeof(prog_data), ¶ms->wm_prog_kernel, ¶ms->wm_prog_data); @@ -102,9 +126,10 @@ struct layer_offset_vs_key { * vertex shader. */ static bool -blorp_params_get_layer_offset_vs(struct blorp_context *blorp, +blorp_params_get_layer_offset_vs(struct blorp_batch *batch, struct blorp_params *params) { + struct blorp_context *blorp = batch->blorp; struct layer_offset_vs_key blorp_key = { .shader_type = BLORP_SHADER_TYPE_LAYER_OFFSET_VS, }; @@ -112,15 +137,14 @@ blorp_params_get_layer_offset_vs(struct blorp_context *blorp, if (params->wm_prog_data) blorp_key.num_inputs = params->wm_prog_data->num_varying_inputs; - if (blorp->lookup_shader(blorp, &blorp_key, sizeof(blorp_key), + if (blorp->lookup_shader(batch, &blorp_key, sizeof(blorp_key), ¶ms->vs_prog_kernel, ¶ms->vs_prog_data)) return true; void *mem_ctx = ralloc_context(NULL); nir_builder b; - nir_builder_init_simple_shader(&b, mem_ctx, MESA_SHADER_VERTEX, NULL); - b.shader->info.name = ralloc_strdup(b.shader, "BLORP-layer-offset-vs"); + blorp_nir_init_shader(&b, mem_ctx, MESA_SHADER_VERTEX, "BLORP-layer-offset-vs"); const struct glsl_type *uvec4_type = glsl_vector_type(GLSL_TYPE_UINT, 4); @@ -166,13 +190,12 @@ blorp_params_get_layer_offset_vs(struct blorp_context *blorp, struct brw_vs_prog_data vs_prog_data; memset(&vs_prog_data, 0, sizeof(vs_prog_data)); - unsigned program_size; const unsigned *program = - blorp_compile_vs(blorp, mem_ctx, b.shader, &vs_prog_data, &program_size); + blorp_compile_vs(blorp, mem_ctx, b.shader, &vs_prog_data); bool result = - blorp->upload_shader(blorp, &blorp_key, sizeof(blorp_key), - program, program_size, + blorp->upload_shader(batch, &blorp_key, sizeof(blorp_key), + program, vs_prog_data.base.base.program_size, &vs_prog_data.base.base, sizeof(vs_prog_data), ¶ms->vs_prog_kernel, ¶ms->vs_prog_data); @@ -308,6 +331,11 @@ blorp_fast_clear(struct blorp_batch *batch, uint32_t level, uint32_t start_layer, uint32_t num_layers, uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1) { + /* Ensure that all layers undergoing the clear have an auxiliary buffer. */ + assert(start_layer + num_layers <= + MAX2(surf->aux_surf->logical_level0_px.depth >> level, + surf->aux_surf->logical_level0_px.array_len)); + struct blorp_params params; blorp_params_init(¶ms); params.num_layers = num_layers; @@ -318,12 +346,12 @@ blorp_fast_clear(struct blorp_batch *batch, params.y1 = y1; memset(¶ms.wm_inputs.clear_color, 0xff, 4*sizeof(float)); - params.fast_clear_op = BLORP_FAST_CLEAR_OP_CLEAR; + params.fast_clear_op = ISL_AUX_OP_FAST_CLEAR; get_fast_clear_rect(batch->blorp->isl_dev, surf->aux_surf, ¶ms.x0, ¶ms.y0, ¶ms.x1, ¶ms.y1); - if (!blorp_params_get_clear_kernel(batch->blorp, ¶ms, true)) + if (!blorp_params_get_clear_kernel(batch, ¶ms, true, false)) return; brw_blorp_surface_info_init(batch->blorp, ¶ms.dst, surf, level, @@ -333,7 +361,7 @@ blorp_fast_clear(struct blorp_batch *batch, batch->blorp->exec(batch, ¶ms); } -static union isl_color_value +union isl_color_value swizzle_color_value(union isl_color_value src, struct isl_swizzle swizzle) { union isl_color_value dst = { .u32 = { 0, } }; @@ -374,9 +402,13 @@ blorp_clear(struct blorp_batch *batch, clear_color = swizzle_color_value(clear_color, swizzle); swizzle = ISL_SWIZZLE_IDENTITY; + bool clear_rgb_as_red = false; if (format == ISL_FORMAT_R9G9B9E5_SHAREDEXP) { clear_color.u32[0] = float3_to_rgb9e5(clear_color.f32); format = ISL_FORMAT_R32_UINT; + } else if (format == ISL_FORMAT_L8_UNORM_SRGB) { + clear_color.f32[0] = util_format_linear_to_srgb_float(clear_color.f32[0]); + format = ISL_FORMAT_R8_UNORM; } else if (format == ISL_FORMAT_A4B4G4R4_UNORM) { /* Broadwell and earlier cannot render to this format so we need to work * around it by swapping the colors around and using B4G4R4A4 instead. @@ -384,6 +416,13 @@ blorp_clear(struct blorp_batch *batch, const struct isl_swizzle ARGB = ISL_SWIZZLE(ALPHA, RED, GREEN, BLUE); clear_color = swizzle_color_value(clear_color, ARGB); format = ISL_FORMAT_B4G4R4A4_UNORM; + } else if (isl_format_get_layout(format)->bpb % 3 == 0) { + clear_rgb_as_red = true; + if (format == ISL_FORMAT_R8G8B8_UNORM_SRGB) { + clear_color.f32[0] = util_format_linear_to_srgb_float(clear_color.f32[0]); + clear_color.f32[1] = util_format_linear_to_srgb_float(clear_color.f32[1]); + clear_color.f32[2] = util_format_linear_to_srgb_float(clear_color.f32[2]); + } } memcpy(¶ms.wm_inputs.clear_color, clear_color.f32, sizeof(float) * 4); @@ -414,11 +453,12 @@ blorp_clear(struct blorp_batch *batch, } } - if (!blorp_params_get_clear_kernel(batch->blorp, ¶ms, - use_simd16_replicated_data)) + if (!blorp_params_get_clear_kernel(batch, ¶ms, + use_simd16_replicated_data, + clear_rgb_as_red)) return; - if (!blorp_ensure_sf_program(batch->blorp, ¶ms)) + if (!blorp_ensure_sf_program(batch, ¶ms)) return; while (num_layers > 0) { @@ -431,20 +471,45 @@ blorp_clear(struct blorp_batch *batch, params.x1 = x1; params.y1 = y1; + if (params.dst.tile_x_sa || params.dst.tile_y_sa) { + assert(params.dst.surf.samples == 1); + assert(num_layers == 1); + params.x0 += params.dst.tile_x_sa; + params.y0 += params.dst.tile_y_sa; + params.x1 += params.dst.tile_x_sa; + params.y1 += params.dst.tile_y_sa; + } + /* The MinLOD and MinimumArrayElement don't work properly for cube maps. * Convert them to a single slice on gen4. */ if (batch->blorp->isl_dev->info->gen == 4 && (params.dst.surf.usage & ISL_SURF_USAGE_CUBE_BIT)) { blorp_surf_convert_to_single_slice(batch->blorp->isl_dev, ¶ms.dst); + } - if (params.dst.tile_x_sa || params.dst.tile_y_sa) { - /* This is gen4 so there is no multisampling and sa == px. */ - params.x0 += params.dst.tile_x_sa; - params.y0 += params.dst.tile_y_sa; - params.x1 += params.dst.tile_x_sa; - params.y1 += params.dst.tile_y_sa; - } + if (clear_rgb_as_red) { + surf_fake_rgb_with_red(batch->blorp->isl_dev, ¶ms.dst); + params.x0 *= 3; + params.x1 *= 3; + } + + if (isl_format_is_compressed(params.dst.surf.format)) { + blorp_surf_convert_to_uncompressed(batch->blorp->isl_dev, ¶ms.dst, + NULL, NULL, NULL, NULL); + //&dst_x, &dst_y, &dst_w, &dst_h); + } + + if (params.dst.tile_x_sa || params.dst.tile_y_sa) { + /* Either we're on gen4 where there is no multisampling or the + * surface is compressed which also implies no multisampling. + * Therefore, sa == px and we don't need to do a conversion. + */ + assert(params.dst.surf.samples == 1); + params.x0 += params.dst.tile_x_sa; + params.y0 += params.dst.tile_y_sa; + params.x1 += params.dst.tile_x_sa; + params.y1 += params.dst.tile_y_sa; } params.num_samples = params.dst.surf.samples; @@ -454,7 +519,46 @@ blorp_clear(struct blorp_batch *batch, * 512 but a maximum 3D texture size is much larger. */ params.num_layers = MIN2(params.dst.view.array_len, num_layers); - batch->blorp->exec(batch, ¶ms); + + const unsigned max_image_width = 16 * 1024; + if (params.dst.surf.logical_level0_px.width > max_image_width) { + /* Clearing an RGB image as red multiplies the surface width by 3 + * so it may now be too wide for the hardware surface limits. We + * have to break the clear up into pieces in order to clear wide + * images. + */ + assert(clear_rgb_as_red); + assert(params.dst.surf.dim == ISL_SURF_DIM_2D); + assert(params.dst.surf.tiling == ISL_TILING_LINEAR); + assert(params.dst.surf.logical_level0_px.depth == 1); + assert(params.dst.surf.logical_level0_px.array_len == 1); + assert(params.dst.surf.levels == 1); + assert(params.dst.surf.samples == 1); + assert(params.dst.tile_x_sa == 0 || params.dst.tile_y_sa == 0); + assert(params.dst.aux_usage == ISL_AUX_USAGE_NONE); + + /* max_image_width rounded down to a multiple of 3 */ + const unsigned max_fake_rgb_width = (max_image_width / 3) * 3; + const unsigned cpp = + isl_format_get_layout(params.dst.surf.format)->bpb / 8; + + params.dst.surf.logical_level0_px.width = max_fake_rgb_width; + params.dst.surf.phys_level0_sa.width = max_fake_rgb_width; + + uint32_t orig_x0 = params.x0, orig_x1 = params.x1; + uint64_t orig_offset = params.dst.addr.offset; + for (uint32_t x = orig_x0; x < orig_x1; x += max_fake_rgb_width) { + /* Offset to the surface. It's easy because we're linear */ + params.dst.addr.offset = orig_offset + x * cpp; + + params.x0 = 0; + params.x1 = MIN2(orig_x1 - x, max_image_width); + + batch->blorp->exec(batch, ¶ms); + } + } else { + batch->blorp->exec(batch, ¶ms); + } start_layer += params.num_layers; num_layers -= params.num_layers; @@ -485,7 +589,7 @@ blorp_clear_depth_stencil(struct blorp_batch *batch, * we disable statistics in 3DSTATE_WM. Give it the usual clear shader * to work around the issue. */ - if (!blorp_params_get_clear_kernel(batch->blorp, ¶ms, false)) + if (!blorp_params_get_clear_kernel(batch, ¶ms, false, false)) return; } @@ -595,6 +699,59 @@ blorp_can_hiz_clear_depth(uint8_t gen, enum isl_format format, return true; } +void +blorp_hiz_clear_depth_stencil(struct blorp_batch *batch, + const struct blorp_surf *depth, + const struct blorp_surf *stencil, + uint32_t level, + uint32_t start_layer, uint32_t num_layers, + uint32_t x0, uint32_t y0, + uint32_t x1, uint32_t y1, + bool clear_depth, float depth_value, + bool clear_stencil, uint8_t stencil_value) +{ + struct blorp_params params; + blorp_params_init(¶ms); + + /* This requires WM_HZ_OP which only exists on gen8+ */ + assert(ISL_DEV_GEN(batch->blorp->isl_dev) >= 8); + + params.hiz_op = ISL_AUX_OP_FAST_CLEAR; + params.num_layers = 1; + + params.x0 = x0; + params.y0 = y0; + params.x1 = x1; + params.y1 = y1; + + for (uint32_t l = 0; l < num_layers; l++) { + const uint32_t layer = start_layer + l; + if (clear_stencil) { + brw_blorp_surface_info_init(batch->blorp, ¶ms.stencil, stencil, + level, layer, + ISL_FORMAT_UNSUPPORTED, true); + params.stencil_mask = 0xff; + params.stencil_ref = stencil_value; + params.num_samples = params.stencil.surf.samples; + } + + if (clear_depth) { + /* If we're clearing depth, we must have HiZ */ + assert(depth && depth->aux_usage == ISL_AUX_USAGE_HIZ); + + brw_blorp_surface_info_init(batch->blorp, ¶ms.depth, depth, + level, layer, + ISL_FORMAT_UNSUPPORTED, true); + params.depth.clear_color.f32[0] = depth_value; + params.depth_format = + isl_format_get_depth_format(depth->surf->format, false); + params.num_samples = params.depth.surf.samples; + } + + batch->blorp->exec(batch, ¶ms); + } +} + /* Given a depth stencil attachment, this function performs a fast depth clear * on a depth portion and a regular clear on the stencil portion. When * performing a fast depth clear on the depth portion, the HiZ buffer is simply @@ -613,7 +770,7 @@ blorp_gen8_hiz_clear_attachments(struct blorp_batch *batch, struct blorp_params params; blorp_params_init(¶ms); params.num_layers = 1; - params.hiz_op = BLORP_HIZ_OP_DEPTH_CLEAR; + params.hiz_op = ISL_AUX_OP_FAST_CLEAR; params.x0 = x0; params.y0 = y0; params.x1 = x1; @@ -672,7 +829,7 @@ blorp_clear_attachments(struct blorp_batch *batch, * is tiled or not, we have to assume it may be linear. This means no * SIMD16_REPDATA for us. :-( */ - if (!blorp_params_get_clear_kernel(batch->blorp, ¶ms, false)) + if (!blorp_params_get_clear_kernel(batch, ¶ms, false, false)) return; } @@ -690,7 +847,7 @@ blorp_clear_attachments(struct blorp_batch *batch, params.stencil_ref = stencil_value; } - if (!blorp_params_get_layer_offset_vs(batch->blorp, ¶ms)) + if (!blorp_params_get_layer_offset_vs(batch, ¶ms)) return; params.vs_inputs.base_layer = start_layer; @@ -700,15 +857,16 @@ blorp_clear_attachments(struct blorp_batch *batch, void blorp_ccs_resolve(struct blorp_batch *batch, - struct blorp_surf *surf, uint32_t level, uint32_t layer, + struct blorp_surf *surf, uint32_t level, + uint32_t start_layer, uint32_t num_layers, enum isl_format format, - enum blorp_fast_clear_op resolve_op) + enum isl_aux_op resolve_op) { struct blorp_params params; - blorp_params_init(¶ms); + blorp_params_init(¶ms); brw_blorp_surface_info_init(batch->blorp, ¶ms.dst, surf, - level, layer, format, true); + level, start_layer, format, true); /* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve": * @@ -740,14 +898,19 @@ blorp_ccs_resolve(struct blorp_batch *batch, params.x1 = ALIGN(params.x1, x_scaledown) / x_scaledown; params.y1 = ALIGN(params.y1, y_scaledown) / y_scaledown; - if (batch->blorp->isl_dev->info->gen >= 9) { - assert(resolve_op == BLORP_FAST_CLEAR_OP_RESOLVE_FULL || - resolve_op == BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL); + if (batch->blorp->isl_dev->info->gen >= 10) { + assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE || + resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE || + resolve_op == ISL_AUX_OP_AMBIGUATE); + } else if (batch->blorp->isl_dev->info->gen >= 9) { + assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE || + resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE); } else { /* Broadwell and earlier do not have a partial resolve */ - assert(resolve_op == BLORP_FAST_CLEAR_OP_RESOLVE_FULL); + assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE); } params.fast_clear_op = resolve_op; + params.num_layers = num_layers; /* Note: there is no need to initialize push constants because it doesn't * matter what data gets dispatched to the render target. However, we must @@ -755,7 +918,292 @@ blorp_ccs_resolve(struct blorp_batch *batch, * color" message. */ - if (!blorp_params_get_clear_kernel(batch->blorp, ¶ms, true)) + if (!blorp_params_get_clear_kernel(batch, ¶ms, true, false)) + return; + + batch->blorp->exec(batch, ¶ms); +} + +static nir_ssa_def * +blorp_nir_bit(nir_builder *b, nir_ssa_def *src, unsigned bit) +{ + return nir_iand(b, nir_ushr(b, src, nir_imm_int(b, bit)), + nir_imm_int(b, 1)); +} + +struct blorp_mcs_partial_resolve_key +{ + enum blorp_shader_type shader_type; + bool indirect_clear_color; + bool int_format; + uint32_t num_samples; +}; + +static bool +blorp_params_get_mcs_partial_resolve_kernel(struct blorp_batch *batch, + struct blorp_params *params) +{ + struct blorp_context *blorp = batch->blorp; + const struct blorp_mcs_partial_resolve_key blorp_key = { + .shader_type = BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE, + .indirect_clear_color = params->dst.clear_color_addr.buffer != NULL, + .int_format = isl_format_has_int_channel(params->dst.view.format), + .num_samples = params->num_samples, + }; + + if (blorp->lookup_shader(batch, &blorp_key, sizeof(blorp_key), + ¶ms->wm_prog_kernel, ¶ms->wm_prog_data)) + return true; + + void *mem_ctx = ralloc_context(NULL); + + nir_builder b; + blorp_nir_init_shader(&b, mem_ctx, MESA_SHADER_FRAGMENT, + "BLORP-mcs-partial-resolve"); + + nir_variable *v_color = + BLORP_CREATE_NIR_INPUT(b.shader, clear_color, glsl_vec4_type()); + + nir_variable *frag_color = + nir_variable_create(b.shader, nir_var_shader_out, + glsl_vec4_type(), "gl_FragColor"); + frag_color->data.location = FRAG_RESULT_COLOR; + + /* Do an MCS fetch and check if it is equal to the magic clear value */ + nir_ssa_def *mcs = + blorp_nir_txf_ms_mcs(&b, nir_f2i32(&b, blorp_nir_frag_coord(&b)), + nir_load_layer_id(&b)); + nir_ssa_def *is_clear = + blorp_nir_mcs_is_clear_color(&b, mcs, blorp_key.num_samples); + + /* If we aren't the clear value, discard. */ + nir_intrinsic_instr *discard = + nir_intrinsic_instr_create(b.shader, nir_intrinsic_discard_if); + discard->src[0] = nir_src_for_ssa(nir_inot(&b, is_clear)); + nir_builder_instr_insert(&b, &discard->instr); + + nir_ssa_def *clear_color = nir_load_var(&b, v_color); + if (blorp_key.indirect_clear_color && blorp->isl_dev->info->gen <= 8) { + /* Gen7-8 clear colors are stored as single 0/1 bits */ + clear_color = nir_vec4(&b, blorp_nir_bit(&b, clear_color, 31), + blorp_nir_bit(&b, clear_color, 30), + blorp_nir_bit(&b, clear_color, 29), + blorp_nir_bit(&b, clear_color, 28)); + + if (!blorp_key.int_format) + clear_color = nir_i2f32(&b, clear_color); + } + nir_store_var(&b, frag_color, clear_color, 0xf); + + struct brw_wm_prog_key wm_key; + brw_blorp_init_wm_prog_key(&wm_key); + wm_key.tex.compressed_multisample_layout_mask = 1; + wm_key.tex.msaa_16 = blorp_key.num_samples == 16; + wm_key.multisample_fbo = true; + + struct brw_wm_prog_data prog_data; + const unsigned *program = + blorp_compile_fs(blorp, mem_ctx, b.shader, &wm_key, false, + &prog_data); + + bool result = + blorp->upload_shader(batch, &blorp_key, sizeof(blorp_key), + program, prog_data.base.program_size, + &prog_data.base, sizeof(prog_data), + ¶ms->wm_prog_kernel, ¶ms->wm_prog_data); + + ralloc_free(mem_ctx); + return result; +} + +void +blorp_mcs_partial_resolve(struct blorp_batch *batch, + struct blorp_surf *surf, + enum isl_format format, + uint32_t start_layer, uint32_t num_layers) +{ + struct blorp_params params; + blorp_params_init(¶ms); + + assert(batch->blorp->isl_dev->info->gen >= 7); + + params.x0 = 0; + params.y0 = 0; + params.x1 = surf->surf->logical_level0_px.width; + params.y1 = surf->surf->logical_level0_px.height; + + brw_blorp_surface_info_init(batch->blorp, ¶ms.src, surf, 0, + start_layer, format, false); + brw_blorp_surface_info_init(batch->blorp, ¶ms.dst, surf, 0, + start_layer, format, true); + + params.num_samples = params.dst.surf.samples; + params.num_layers = num_layers; + params.dst_clear_color_as_input = surf->clear_color_addr.buffer != NULL; + + memcpy(¶ms.wm_inputs.clear_color, + surf->clear_color.f32, sizeof(float) * 4); + + if (!blorp_params_get_mcs_partial_resolve_kernel(batch, ¶ms)) + return; + + batch->blorp->exec(batch, ¶ms); +} + +/** Clear a CCS to the "uncompressed" state + * + * This pass is the CCS equivalent of a "HiZ resolve". It sets the CCS values + * for a given layer/level of a surface to 0x0 which is the "uncompressed" + * state which tells the sampler to go look at the main surface. + */ +void +blorp_ccs_ambiguate(struct blorp_batch *batch, + struct blorp_surf *surf, + uint32_t level, uint32_t layer) +{ + if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 10) { + /* On gen10 and above, we have a hardware resolve op for this */ + return blorp_ccs_resolve(batch, surf, level, layer, 1, + surf->surf->format, ISL_AUX_OP_AMBIGUATE); + } + + struct blorp_params params; + blorp_params_init(¶ms); + + assert(ISL_DEV_GEN(batch->blorp->isl_dev) >= 7); + + const struct isl_format_layout *aux_fmtl = + isl_format_get_layout(surf->aux_surf->format); + assert(aux_fmtl->txc == ISL_TXC_CCS); + + params.dst = (struct brw_blorp_surface_info) { + .enabled = true, + .addr = surf->aux_addr, + .view = { + .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT, + .format = ISL_FORMAT_R32G32B32A32_UINT, + .base_level = 0, + .base_array_layer = 0, + .levels = 1, + .array_len = 1, + .swizzle = ISL_SWIZZLE_IDENTITY, + }, + }; + + uint32_t z = 0; + if (surf->surf->dim == ISL_SURF_DIM_3D) { + z = layer; + layer = 0; + } + + uint32_t offset_B, x_offset_el, y_offset_el; + isl_surf_get_image_offset_el(surf->aux_surf, level, layer, z, + &x_offset_el, &y_offset_el); + isl_tiling_get_intratile_offset_el(surf->aux_surf->tiling, aux_fmtl->bpb, + surf->aux_surf->row_pitch_B, + x_offset_el, y_offset_el, + &offset_B, &x_offset_el, &y_offset_el); + params.dst.addr.offset += offset_B; + + const uint32_t width_px = + minify(surf->aux_surf->logical_level0_px.width, level); + const uint32_t height_px = + minify(surf->aux_surf->logical_level0_px.height, level); + const uint32_t width_el = DIV_ROUND_UP(width_px, aux_fmtl->bw); + const uint32_t height_el = DIV_ROUND_UP(height_px, aux_fmtl->bh); + + struct isl_tile_info ccs_tile_info; + isl_surf_get_tile_info(surf->aux_surf, &ccs_tile_info); + + /* We're going to map it as a regular RGBA32_UINT surface. We need to + * downscale a good deal. We start by computing the area on the CCS to + * clear in units of Y-tiled cache lines. + */ + uint32_t x_offset_cl, y_offset_cl, width_cl, height_cl; + if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 8) { + /* From the Sky Lake PRM Vol. 12 in the section on planes: + * + * "The Color Control Surface (CCS) contains the compression status + * of the cache-line pairs. The compression state of the cache-line + * pair is specified by 2 bits in the CCS. Each CCS cache-line + * represents an area on the main surface of 16x16 sets of 128 byte + * Y-tiled cache-line-pairs. CCS is always Y tiled." + * + * Each 2-bit surface element in the CCS corresponds to a single + * cache-line pair in the main surface. This means that 16x16 el block + * in the CCS maps to a Y-tiled cache line. Fortunately, CCS layouts + * are calculated with a very large alignment so we can round up to a + * whole cache line without worrying about overdraw. + */ + + /* On Broadwell and above, a CCS tile is the same as a Y tile when + * viewed at the cache-line granularity. Fortunately, the horizontal + * and vertical alignment requirements of the CCS are such that we can + * align to an entire cache line without worrying about crossing over + * from one LOD to another. + */ + const uint32_t x_el_per_cl = ccs_tile_info.logical_extent_el.w / 8; + const uint32_t y_el_per_cl = ccs_tile_info.logical_extent_el.h / 8; + assert(surf->aux_surf->image_alignment_el.w % x_el_per_cl == 0); + assert(surf->aux_surf->image_alignment_el.h % y_el_per_cl == 0); + + assert(x_offset_el % x_el_per_cl == 0); + assert(y_offset_el % y_el_per_cl == 0); + x_offset_cl = x_offset_el / x_el_per_cl; + y_offset_cl = y_offset_el / y_el_per_cl; + width_cl = DIV_ROUND_UP(width_el, x_el_per_cl); + height_cl = DIV_ROUND_UP(height_el, y_el_per_cl); + } else { + /* On gen7, the CCS tiling is not so nice. However, there we are + * guaranteed that we only have a single level and slice so we don't + * have to worry about it and can just align to a whole tile. + */ + assert(surf->aux_surf->logical_level0_px.depth == 1); + assert(surf->aux_surf->logical_level0_px.array_len == 1); + assert(x_offset_el == 0 && y_offset_el == 0); + const uint32_t width_tl = + DIV_ROUND_UP(width_el, ccs_tile_info.logical_extent_el.w); + const uint32_t height_tl = + DIV_ROUND_UP(height_el, ccs_tile_info.logical_extent_el.h); + x_offset_cl = 0; + y_offset_cl = 0; + width_cl = width_tl * 8; + height_cl = height_tl * 8; + } + + /* We're going to use a RGBA32 format so as to write data as quickly as + * possible. A y-tiled cache line will then be 1x4 px. + */ + const uint32_t x_offset_rgba_px = x_offset_cl; + const uint32_t y_offset_rgba_px = y_offset_cl * 4; + const uint32_t width_rgba_px = width_cl; + const uint32_t height_rgba_px = height_cl * 4; + + MAYBE_UNUSED bool ok = + isl_surf_init(batch->blorp->isl_dev, ¶ms.dst.surf, + .dim = ISL_SURF_DIM_2D, + .format = ISL_FORMAT_R32G32B32A32_UINT, + .width = width_rgba_px + x_offset_rgba_px, + .height = height_rgba_px + y_offset_rgba_px, + .depth = 1, + .levels = 1, + .array_len = 1, + .samples = 1, + .row_pitch_B = surf->aux_surf->row_pitch_B, + .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT, + .tiling_flags = ISL_TILING_Y0_BIT); + assert(ok); + + params.x0 = x_offset_rgba_px; + params.y0 = y_offset_rgba_px; + params.x1 = x_offset_rgba_px + width_rgba_px; + params.y1 = y_offset_rgba_px + height_rgba_px; + + /* A CCS value of 0 means "uncompressed." */ + memset(¶ms.wm_inputs.clear_color, 0, + sizeof(params.wm_inputs.clear_color)); + + if (!blorp_params_get_clear_kernel(batch, ¶ms, true, false)) return; batch->blorp->exec(batch, ¶ms);