X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fintel%2Fcompiler%2Fbrw_compiler.c;h=e58ed67900b1055f9914d3a1a630d23a7c306c61;hb=e2b6ccbdadd9438eab60ba7dbf8c0d870079c839;hp=536dc86ab78954ba07f43ce86b853fd5e73586f9;hpb=6a9e39d44b06076d6ff444b59f2b39ffe222cd2d;p=mesa.git diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index 536dc86ab78..e58ed67900b 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_compiler.c @@ -34,9 +34,7 @@ .lower_fdiv = true, \ .lower_scmp = true, \ .lower_flrp16 = true, \ - .lower_fmod16 = true, \ - .lower_fmod32 = true, \ - .lower_fmod64 = false, \ + .lower_fmod = true, \ .lower_bitfield_extract = true, \ .lower_bitfield_insert = true, \ .lower_uadd_carry = true, \ @@ -49,9 +47,13 @@ .vectorize_io = true, \ .use_interpolated_input_intrinsics = true, \ .vertex_id_zero_based = true, \ - .lower_base_vertex = true + .lower_base_vertex = true, \ + .use_scoped_barrier = true, \ + .support_8bit_alu = true, \ + .support_16bit_alu = true #define COMMON_SCALAR_OPTIONS \ + .lower_to_scalar = true, \ .lower_pack_half_2x16 = true, \ .lower_pack_snorm_2x16 = true, \ .lower_pack_snorm_4x8 = true, \ @@ -62,6 +64,9 @@ .lower_unpack_snorm_4x8 = true, \ .lower_unpack_unorm_2x16 = true, \ .lower_unpack_unorm_4x8 = true, \ + .lower_usub_sat64 = true, \ + .lower_hadd64 = true, \ + .lower_bfe_with_two_constants = true, \ .max_unroll_iterations = 32 static const struct nir_shader_compiler_options scalar_nir_options = { @@ -84,6 +89,7 @@ static const struct nir_shader_compiler_options vector_nir_options = { .lower_unpack_unorm_2x16 = true, .lower_extract_byte = true, .lower_extract_word = true, + .intel_vec4 = true, .max_unroll_iterations = 32, }; @@ -101,7 +107,8 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo) compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false); compiler->use_tcs_8_patch = - devinfo->gen >= 9 && (INTEL_DEBUG & DEBUG_TCS_EIGHT_PATCH); + devinfo->gen >= 12 || + (devinfo->gen >= 9 && (INTEL_DEBUG & DEBUG_TCS_EIGHT_PATCH)); if (devinfo->gen >= 10) { /* We don't support vec4 mode on Cannonlake. */ @@ -134,17 +141,12 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo) nir_lower_dceil | nir_lower_dfract | nir_lower_dround_even | - nir_lower_dmod; - - if (!devinfo->has_64bit_types || (INTEL_DEBUG & DEBUG_SOFT64)) { - int64_options |= nir_lower_mov64 | - nir_lower_icmp64 | - nir_lower_iadd64 | - nir_lower_iabs64 | - nir_lower_ineg64 | - nir_lower_logic64 | - nir_lower_minmax64 | - nir_lower_shift64; + nir_lower_dmod | + nir_lower_dsub | + nir_lower_ddiv; + + if (!devinfo->has_64bit_float || (INTEL_DEBUG & DEBUG_SOFT64)) { + int64_options |= (nir_lower_int64_options)~0; fp64_options |= nir_lower_fp64_full_software; } @@ -183,9 +185,16 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo) */ nir_options->lower_ffma = devinfo->gen < 6; nir_options->lower_flrp32 = devinfo->gen < 6 || devinfo->gen >= 11; + nir_options->lower_fpow = devinfo->gen >= 12; + + nir_options->lower_rotate = devinfo->gen < 11; + nir_options->lower_bitfield_reverse = devinfo->gen < 7; nir_options->lower_int64_options = int64_options; nir_options->lower_doubles_options = fp64_options; + + nir_options->unify_interfaces = i < MESA_SHADER_FRAGMENT; + compiler->glsl_compiler_options[i].NirOptions = nir_options; compiler->glsl_compiler_options[i].ClampBlockIndicesToArrayBounds = true; @@ -231,19 +240,13 @@ brw_get_compiler_config_value(const struct brw_compiler *compiler) unsigned brw_prog_data_size(gl_shader_stage stage) { - STATIC_ASSERT(MESA_SHADER_VERTEX == 0); - STATIC_ASSERT(MESA_SHADER_TESS_CTRL == 1); - STATIC_ASSERT(MESA_SHADER_TESS_EVAL == 2); - STATIC_ASSERT(MESA_SHADER_GEOMETRY == 3); - STATIC_ASSERT(MESA_SHADER_FRAGMENT == 4); - STATIC_ASSERT(MESA_SHADER_COMPUTE == 5); static const size_t stage_sizes[] = { - sizeof(struct brw_vs_prog_data), - sizeof(struct brw_tcs_prog_data), - sizeof(struct brw_tes_prog_data), - sizeof(struct brw_gs_prog_data), - sizeof(struct brw_wm_prog_data), - sizeof(struct brw_cs_prog_data), + [MESA_SHADER_VERTEX] = sizeof(struct brw_vs_prog_data), + [MESA_SHADER_TESS_CTRL] = sizeof(struct brw_tcs_prog_data), + [MESA_SHADER_TESS_EVAL] = sizeof(struct brw_tes_prog_data), + [MESA_SHADER_GEOMETRY] = sizeof(struct brw_gs_prog_data), + [MESA_SHADER_FRAGMENT] = sizeof(struct brw_wm_prog_data), + [MESA_SHADER_COMPUTE] = sizeof(struct brw_cs_prog_data), }; assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes)); return stage_sizes[stage]; @@ -253,30 +256,13 @@ unsigned brw_prog_key_size(gl_shader_stage stage) { static const size_t stage_sizes[] = { - sizeof(struct brw_vs_prog_key), - sizeof(struct brw_tcs_prog_key), - sizeof(struct brw_tes_prog_key), - sizeof(struct brw_gs_prog_key), - sizeof(struct brw_wm_prog_key), - sizeof(struct brw_cs_prog_key), + [MESA_SHADER_VERTEX] = sizeof(struct brw_vs_prog_key), + [MESA_SHADER_TESS_CTRL] = sizeof(struct brw_tcs_prog_key), + [MESA_SHADER_TESS_EVAL] = sizeof(struct brw_tes_prog_key), + [MESA_SHADER_GEOMETRY] = sizeof(struct brw_gs_prog_key), + [MESA_SHADER_FRAGMENT] = sizeof(struct brw_wm_prog_key), + [MESA_SHADER_COMPUTE] = sizeof(struct brw_cs_prog_key), }; assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes)); return stage_sizes[stage]; } - -void -brw_prog_key_set_id(union brw_any_prog_key *key, - gl_shader_stage stage, - unsigned id) -{ - static const unsigned stage_offsets[] = { - offsetof(struct brw_vs_prog_key, program_string_id), - offsetof(struct brw_tcs_prog_key, program_string_id), - offsetof(struct brw_tes_prog_key, program_string_id), - offsetof(struct brw_gs_prog_key, program_string_id), - offsetof(struct brw_wm_prog_key, program_string_id), - offsetof(struct brw_cs_prog_key, program_string_id), - }; - assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_offsets)); - *(unsigned*)((uint8_t*)key + stage_offsets[stage]) = id; -}