X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fintel%2Fcompiler%2Fbrw_compiler.h;h=ccbb5cc640903e87ab68642868250ae87cf183bf;hb=22b512ea5b11c3b02f488d7143556eb0ef8c1303;hp=1045ef5076fd4ae57ff0ed81f9eba4ff95e39091;hpb=0edb58a84eb4a2b74b1ce55fea9dc06386c56bf6;p=mesa.git

diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h
index 1045ef5076f..ccbb5cc6409 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -125,6 +125,12 @@ struct brw_compiler {
     * back-end compiler.
     */
    bool compact_params;
+
+   /**
+    * Whether or not the driver wants variable group size to be lowered by the
+    * back-end compiler.
+    */
+   bool lower_variable_group_size;
 };
 
 /**
@@ -204,6 +210,8 @@ struct brw_sampler_prog_key_data {
    uint32_t xy_uxvx_image_mask;
    uint32_t ayuv_image_mask;
    uint32_t xyuv_image_mask;
+   uint32_t bt709_mask;
+   uint32_t bt2020_mask;
 
    /* Scale factor for each texture. */
    float scale_factors[32];
@@ -451,6 +459,7 @@ struct brw_wm_prog_key {
    bool high_quality_derivatives:1;
    bool force_dual_color_blend:1;
    bool coherent_fb_fetch:1;
+   bool ignore_sample_mask_out:1;
 
    uint8_t color_outputs_valid;
    uint64_t input_slots_valid;
@@ -917,8 +926,20 @@ struct brw_cs_prog_data {
    struct brw_stage_prog_data base;
 
    unsigned local_size[3];
-   unsigned simd_size;
    unsigned slm_size;
+
+   /* Program offsets for the 8/16/32 SIMD variants.  Multiple variants are
+    * kept when using variable group size, and the right one can only be
+    * decided at dispatch time.
+    */
+   unsigned prog_offset[3];
+
+   /* Bitmask indicating which program offsets are valid. */
+   unsigned prog_mask;
+
+   /* Bitmask indicating which programs have spilled. */
+   unsigned prog_spilled;
+
    bool uses_barrier;
    bool uses_num_work_groups;
 
@@ -936,6 +957,18 @@ struct brw_cs_prog_data {
    } binding_table;
 };
 
+static inline uint32_t
+brw_cs_prog_data_prog_offset(const struct brw_cs_prog_data *prog_data,
+                             unsigned dispatch_width)
+{
+   assert(dispatch_width == 8 ||
+          dispatch_width == 16 ||
+          dispatch_width == 32);
+   const unsigned index = dispatch_width / 16;
+   assert(prog_data->prog_mask & (1 << index));
+   return prog_data->prog_offset[index];
+}
+
 /**
  * Enum representing the i965-specific vertex results that don't correspond
  * exactly to any element of gl_varying_slot.  The values of this enum are
@@ -1494,6 +1527,24 @@ unsigned
 brw_cs_push_const_total_size(const struct brw_cs_prog_data *cs_prog_data,
                              unsigned threads);
 
+unsigned
+brw_cs_simd_size_for_group_size(const struct gen_device_info *devinfo,
+                                const struct brw_cs_prog_data *cs_prog_data,
+                                unsigned group_size);
+
+/**
+ * Calculate the RightExecutionMask field used in GPGPU_WALKER.
+ */
+static inline unsigned
+brw_cs_right_mask(unsigned group_size, unsigned simd_size)
+{
+   const uint32_t remainder = group_size & (simd_size - 1);
+   if (remainder > 0)
+      return ~0u >> (32 - remainder);
+   else
+      return ~0u >> (32 - simd_size);
+}
+
 /**
  * Return true if the given shader stage is dispatched contiguously by the
  * relevant fixed function starting from channel 0 of the SIMD thread, which