X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fintel%2Fcompiler%2Fbrw_disasm.c;h=8b7047db00faff45ede0b817068506e9cf7cefa3;hb=95d8b4ac0bbef31aa99e21ee6ce18eb09c05d934;hp=04efa965cef71c27892970515b40e55d5b89116f;hpb=5211159b5b469409ac9c6d8b52535c5bb544c508;p=mesa.git diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c index 04efa965cef..8b7047db00f 100644 --- a/src/intel/compiler/brw_disasm.c +++ b/src/intel/compiler/brw_disasm.c @@ -1339,9 +1339,18 @@ imm(FILE *file, const struct gen_device_info *devinfo, enum brw_reg_type type, format(file, "0x%08xV", brw_inst_imm_ud(devinfo, inst)); break; case BRW_REGISTER_TYPE_F: - format(file, "0x%"PRIx64"F", brw_inst_bits(inst, 127, 96)); - pad(file, 48); - format(file, " /* %-gF */", brw_inst_imm_f(devinfo, inst)); + /* The DIM instruction's src0 uses an F type but contains a + * 64-bit immediate + */ + if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_DIM) { + format(file, "0x%"PRIx64"F", brw_inst_bits(inst, 127, 64)); + pad(file, 48); + format(file, "/* %-gF */", brw_inst_imm_df(devinfo, inst)); + } else { + format(file, "0x%"PRIx64"F", brw_inst_bits(inst, 127, 96)); + pad(file, 48); + format(file, " /* %-gF */", brw_inst_imm_f(devinfo, inst)); + } break; case BRW_REGISTER_TYPE_DF: format(file, "0x%016"PRIx64"DF", brw_inst_bits(inst, 127, 64)); @@ -1661,7 +1670,8 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo, format(file, "Pop: %"PRIu64, brw_inst_gen4_pop_count(devinfo, inst)); } else if (devinfo->gen < 6 && (opcode == BRW_OPCODE_IF || opcode == BRW_OPCODE_IFF || - opcode == BRW_OPCODE_HALT)) { + opcode == BRW_OPCODE_HALT || + opcode == BRW_OPCODE_WHILE)) { pad(file, 16); format(file, "Jump: %d", brw_inst_gen4_jump_count(devinfo, inst)); } else if (devinfo->gen < 6 && opcode == BRW_OPCODE_ENDIF) {