X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fintel%2Fcompiler%2Fbrw_fs_nir.cpp;h=49fafe1417a44b4d9ad3d0582bf5d670f4eb8a99;hb=ed9ac3d60cffc60d97f5ddc168643ed7656224bf;hp=15df3dc77634b82999bd21652b024a5aa555a26b;hpb=675d7b19a9aece0ea674eadba20ec2b01c86de6e;p=mesa.git diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 15df3dc7763..49fafe1417a 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -59,7 +59,7 @@ fs_visitor::nir_setup_outputs() * allocating them. With ARB_enhanced_layouts, multiple output variables * may occupy the same slot, but have different type sizes. */ - nir_foreach_variable(var, &nir->outputs) { + nir_foreach_shader_out_variable(var, nir) { const int loc = var->data.driver_location; const unsigned var_vec4s = var->data.compact ? DIV_ROUND_UP(glsl_get_length(var->type), 4) @@ -100,7 +100,7 @@ fs_visitor::nir_setup_uniforms() uniforms = nir->num_uniforms / 4; - if (stage == MESA_SHADER_COMPUTE) { + if (stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL) { /* Add uniforms for builtins after regular NIR uniforms. */ assert(uniforms == prog_data->nr_params); @@ -184,7 +184,8 @@ emit_system_values_block(nir_block *block, fs_visitor *v) break; case nir_intrinsic_load_work_group_id: - assert(v->stage == MESA_SHADER_COMPUTE); + assert(v->stage == MESA_SHADER_COMPUTE || + v->stage == MESA_SHADER_KERNEL); reg = &v->nir_system_values[SYSTEM_VALUE_WORK_GROUP_ID]; if (reg->file == BAD_FILE) *reg = *v->emit_cs_work_group_id_setup(); @@ -489,6 +490,7 @@ fs_visitor::nir_emit_instr(nir_instr *instr) nir_emit_fs_intrinsic(abld, nir_instr_as_intrinsic(instr)); break; case MESA_SHADER_COMPUTE: + case MESA_SHADER_KERNEL: nir_emit_cs_intrinsic(abld, nir_instr_as_intrinsic(instr)); break; default: @@ -750,6 +752,8 @@ fs_visitor::prepare_alu_destination_and_sources(const fs_builder &bld, case nir_op_vec2: case nir_op_vec3: case nir_op_vec4: + case nir_op_vec8: + case nir_op_vec16: return result; default: break; @@ -1000,14 +1004,16 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, unsigned execution_mode = bld.shader->nir->info.float_controls_execution_mode; - fs_reg op[4]; + fs_reg op[NIR_MAX_VEC_COMPONENTS]; fs_reg result = prepare_alu_destination_and_sources(bld, instr, op, need_dest); switch (instr->op) { case nir_op_mov: case nir_op_vec2: case nir_op_vec3: - case nir_op_vec4: { + case nir_op_vec4: + case nir_op_vec8: + case nir_op_vec16: { fs_reg temp = result; bool need_extra_copy = false; for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) { @@ -1024,10 +1030,10 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, continue; if (instr->op == nir_op_mov) { - inst = bld.MOV(offset(temp, bld, i), + bld.MOV(offset(temp, bld, i), offset(op[0], bld, instr->src[0].swizzle[i])); } else { - inst = bld.MOV(offset(temp, bld, i), + bld.MOV(offset(temp, bld, i), offset(op[i], bld, instr->src[i].swizzle[0])); } } @@ -1383,7 +1389,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, case nir_op_flt32: case nir_op_fge32: case nir_op_feq32: - case nir_op_fne32: { + case nir_op_fneu32: { fs_reg dest = result; const uint32_t bit_size = nir_src_bit_size(instr->src[0].src); @@ -3433,7 +3439,7 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder &bld, alu->op != nir_op_bcsel && (devinfo->gen > 5 || (alu->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) != BRW_NIR_BOOLEAN_NEEDS_RESOLVE || - alu->op == nir_op_fne32 || alu->op == nir_op_feq32 || + alu->op == nir_op_fneu32 || alu->op == nir_op_feq32 || alu->op == nir_op_flt32 || alu->op == nir_op_fge32 || alu->op == nir_op_ine32 || alu->op == nir_op_ieq32 || alu->op == nir_op_ilt32 || alu->op == nir_op_ige32 || @@ -3714,7 +3720,7 @@ void fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr) { - assert(stage == MESA_SHADER_COMPUTE); + assert(stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL); struct brw_cs_prog_data *cs_prog_data = brw_cs_prog_data(prog_data); fs_reg dest; @@ -3792,7 +3798,7 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld, case nir_intrinsic_load_shared: { assert(devinfo->gen >= 7); - assert(stage == MESA_SHADER_COMPUTE); + assert(stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL); const unsigned bit_size = nir_dest_bit_size(instr->dest); fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; @@ -3828,7 +3834,7 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld, case nir_intrinsic_store_shared: { assert(devinfo->gen >= 7); - assert(stage == MESA_SHADER_COMPUTE); + assert(stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL); const unsigned bit_size = nir_src_bit_size(instr->src[0]); fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; @@ -4164,6 +4170,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr BRW_REGISTER_TYPE_UD); image = bld.emit_uniformize(image); + assert(nir_src_as_uint(instr->src[1]) == 0); + fs_reg srcs[TEX_LOGICAL_NUM_SRCS]; if (instr->intrinsic == nir_intrinsic_image_size) srcs[TEX_LOGICAL_SRC_SURFACE] = image; @@ -4280,7 +4288,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr break; } - if (stage != MESA_SHADER_COMPUTE) + if (stage != MESA_SHADER_COMPUTE && stage != MESA_SHADER_KERNEL) slm_fence = false; /* If the workgroup fits in a single HW thread, the messages for SLM are @@ -4546,7 +4554,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr break; } - case nir_intrinsic_load_global: { + case nir_intrinsic_load_global: + case nir_intrinsic_load_global_constant: { assert(devinfo->gen >= 8); assert(nir_dest_bit_size(instr->dest) <= 32); @@ -4814,7 +4823,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr /* Read the vector */ assert(nir_dest_num_components(instr->dest) == 1); assert(nir_dest_bit_size(instr->dest) <= 32); - assert(nir_intrinsic_align(instr) > 1); + assert(nir_intrinsic_align(instr) > 0); if (nir_dest_bit_size(instr->dest) >= 4 && nir_intrinsic_align(instr) >= 4) { /* The offset for a DWORD scattered message is in dwords. */