X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fintel%2Fcompiler%2Fbrw_reg.h;h=620b8722d92534e0c814c474e0b1fd7e7936931c;hb=5c5555a862754a5b43fee2abf4fc34e888d22a06;hp=ec1045b612a4d807a168e86aea95ab9bf39bbfa7;hpb=1cb210f4bc412a9c1fef12e05ea9d9fe8995f4d5;p=mesa.git diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h index ec1045b612a..620b8722d92 100644 --- a/src/intel/compiler/brw_reg.h +++ b/src/intel/compiler/brw_reg.h @@ -43,7 +43,7 @@ #define BRW_REG_H #include -#include "main/compiler.h" +#include "util/compiler.h" #include "main/macros.h" #include "program/prog_instruction.h" #include "brw_eu_defines.h" @@ -221,15 +221,15 @@ struct brw_reg { unsigned negate:1; /* source only */ unsigned abs:1; /* source only */ unsigned address_mode:1; /* relative addressing, hopefully! */ - unsigned pad0:1; + unsigned pad0:17; unsigned subnr:5; /* :1 in align16 */ - unsigned nr:16; }; uint32_t bits; }; union { struct { + unsigned nr; unsigned swizzle:8; /* src only, align16 only */ unsigned writemask:4; /* dest only, align16 only */ int indirect_offset:10; /* relative addressing offset */ @@ -251,8 +251,57 @@ struct brw_reg { static inline bool brw_regs_equal(const struct brw_reg *a, const struct brw_reg *b) { - const bool df = a->type == BRW_REGISTER_TYPE_DF && a->file == IMM; - return a->bits == b->bits && (df ? a->u64 == b->u64 : a->ud == b->ud); + return a->bits == b->bits && a->u64 == b->u64; +} + +static inline bool +brw_regs_negative_equal(const struct brw_reg *a, const struct brw_reg *b) +{ + if (a->file == IMM) { + if (a->bits != b->bits) + return false; + + switch ((enum brw_reg_type) a->type) { + case BRW_REGISTER_TYPE_UQ: + case BRW_REGISTER_TYPE_Q: + return a->d64 == -b->d64; + case BRW_REGISTER_TYPE_DF: + return a->df == -b->df; + case BRW_REGISTER_TYPE_UD: + case BRW_REGISTER_TYPE_D: + return a->d == -b->d; + case BRW_REGISTER_TYPE_F: + return a->f == -b->f; + case BRW_REGISTER_TYPE_VF: + /* It is tempting to treat 0 as a negation of 0 (and -0 as a negation + * of -0). There are occasions where 0 or -0 is used and the exact + * bit pattern is desired. At the very least, changing this to allow + * 0 as a negation of 0 causes some fp64 tests to fail on IVB. + */ + return a->ud == (b->ud ^ 0x80808080); + case BRW_REGISTER_TYPE_UW: + case BRW_REGISTER_TYPE_W: + case BRW_REGISTER_TYPE_UV: + case BRW_REGISTER_TYPE_V: + case BRW_REGISTER_TYPE_HF: + /* FINISHME: Implement support for these types once there is + * something in the compiler that can generate them. Until then, + * they cannot be tested. + */ + return false; + case BRW_REGISTER_TYPE_UB: + case BRW_REGISTER_TYPE_B: + case BRW_REGISTER_TYPE_NF: + default: + unreachable("not reached"); + } + } else { + struct brw_reg tmp = *a; + + tmp.negate = !tmp.negate; + + return brw_regs_equal(&tmp, b); + } } struct brw_indirect { @@ -269,6 +318,7 @@ type_sz(unsigned type) case BRW_REGISTER_TYPE_UQ: case BRW_REGISTER_TYPE_Q: case BRW_REGISTER_TYPE_DF: + case BRW_REGISTER_TYPE_NF: return 8; case BRW_REGISTER_TYPE_UD: case BRW_REGISTER_TYPE_D: @@ -326,6 +376,15 @@ brw_int_type(unsigned sz, bool is_signed) } } +static inline bool +type_is_unsigned_int(enum brw_reg_type tp) +{ + return tp == BRW_REGISTER_TYPE_UB || + tp == BRW_REGISTER_TYPE_UW || + tp == BRW_REGISTER_TYPE_UD || + tp == BRW_REGISTER_TYPE_UQ; +} + /** * Construct a brw_reg. * \param file one of the BRW_x_REGISTER_FILE values @@ -589,6 +648,14 @@ brw_imm_df(double df) return imm; } +static inline struct brw_reg +brw_imm_u64(uint64_t u64) +{ + struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UQ); + imm.u64 = u64; + return imm; +} + static inline struct brw_reg brw_imm_f(float f) { @@ -647,7 +714,7 @@ static inline struct brw_reg brw_imm_w(int16_t w) { struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W); - imm.d = w | (w << 16); + imm.ud = (uint16_t)w | (uint32_t)(uint16_t)w << 16; return imm; } @@ -774,6 +841,12 @@ brw_address_reg(unsigned subnr) return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_ADDRESS, subnr); } +static inline struct brw_reg +brw_tdr_reg(void) +{ + return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_TDR, 0); +} + /* If/else instructions break in align16 mode if writemask & swizzle * aren't xyzw. This goes against the convention for other scalar * regs: @@ -810,6 +883,12 @@ brw_notification_reg(void) WRITEMASK_X); } +static inline struct brw_reg +brw_cr0_reg(unsigned subnr) +{ + return brw_ud1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_CONTROL, subnr); +} + static inline struct brw_reg brw_sr0_reg(unsigned subnr) { @@ -830,6 +909,13 @@ brw_flag_reg(int reg, int subreg) BRW_ARF_FLAG + reg, subreg); } +static inline struct brw_reg +brw_flag_subreg(unsigned subreg) +{ + return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, + BRW_ARF_FLAG + subreg / 2, subreg % 2); +} + /** * Return the mask register present in Gen4-5, or the related register present * in Gen7.5 and later hardware referred to as "channel enable" register in @@ -853,6 +939,21 @@ brw_dmask_reg() return brw_sr0_reg(2); } +static inline struct brw_reg +brw_mask_stack_reg(unsigned subnr) +{ + return suboffset(retype(brw_vec16_reg(BRW_ARCHITECTURE_REGISTER_FILE, + BRW_ARF_MASK_STACK, 0), + BRW_REGISTER_TYPE_UB), subnr); +} + +static inline struct brw_reg +brw_mask_stack_depth_reg(unsigned subnr) +{ + return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, + BRW_ARF_MASK_STACK_DEPTH, subnr); +} + static inline struct brw_reg brw_message_reg(unsigned nr) { @@ -900,7 +1001,7 @@ static inline struct brw_reg spread(struct brw_reg reg, unsigned s) { if (s) { - assert(_mesa_is_pow_two(s)); + assert(util_is_power_of_two_nonzero(s)); if (reg.hstride) reg.hstride += cvt(s) - 1;