X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fintel%2Fcompiler%2Fbrw_vec4.cpp;h=ee91be0a7ab6469ff4a12c8b83209d4cf70630af;hb=HEAD;hp=514fab10820af7bff86c00aaf43aab4d6e81d3f3;hpb=48dfb30f9231c22a6af6885dbc9ef86dc2edde1e;p=mesa.git diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp index 514fab10820..ee91be0a7ab 100644 --- a/src/intel/compiler/brw_vec4.cpp +++ b/src/intel/compiler/brw_vec4.cpp @@ -147,7 +147,7 @@ dst_reg::equals(const dst_reg &r) const } bool -vec4_instruction::is_send_from_grf() +vec4_instruction::is_send_from_grf() const { switch (opcode) { case SHADER_OPCODE_SHADER_TIME_ADD: @@ -326,13 +326,13 @@ vec4_instruction::can_change_types() const * instruction -- the generate_* functions generate additional MOVs * for setup. */ -int -vec4_visitor::implied_mrf_writes(vec4_instruction *inst) +unsigned +vec4_instruction::implied_mrf_writes() const { - if (inst->mlen == 0 || inst->is_send_from_grf()) + if (mlen == 0 || is_send_from_grf()) return 0; - switch (inst->opcode) { + switch (opcode) { case SHADER_OPCODE_RCP: case SHADER_OPCODE_RSQ: case SHADER_OPCODE_SQRT: @@ -376,7 +376,7 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst) case SHADER_OPCODE_TG4_OFFSET: case SHADER_OPCODE_SAMPLEINFO: case SHADER_OPCODE_GET_BUFFER_SIZE: - return inst->header_size; + return header_size; default: unreachable("not reached"); } @@ -1253,8 +1253,7 @@ vec4_visitor::opt_register_coalesce() { bool progress = false; int next_ip = 0; - - calculate_live_intervals(); + const vec4_live_variables &live = live_analysis.require(); foreach_block_and_inst_safe (block, vec4_instruction, inst, cfg) { int ip = next_ip; @@ -1296,8 +1295,7 @@ vec4_visitor::opt_register_coalesce() /* Can't coalesce this GRF if someone else was going to * read it later. */ - if (live_intervals->var_range_end( - var_from_reg(alloc, dst_reg(inst->src[0])), 8) > ip) + if (live.var_range_end(var_from_reg(alloc, dst_reg(inst->src[0])), 8) > ip) continue; /* We need to check interference with the final destination between this @@ -1607,15 +1605,15 @@ vec4_visitor::split_virtual_grfs() } void -vec4_visitor::dump_instruction(backend_instruction *be_inst) +vec4_visitor::dump_instruction(const backend_instruction *be_inst) const { dump_instruction(be_inst, stderr); } void -vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file) +vec4_visitor::dump_instruction(const backend_instruction *be_inst, FILE *file) const { - vec4_instruction *inst = (vec4_instruction *)be_inst; + const vec4_instruction *inst = (const vec4_instruction *)be_inst; if (inst->predicate) { fprintf(file, "(%cf%d.%d%s) ", @@ -2672,6 +2670,7 @@ void vec4_visitor::invalidate_analysis(brw::analysis_dependency_class c) { backend_shader::invalidate_analysis(c); + live_analysis.invalidate(c); } bool @@ -2854,13 +2853,13 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data, void *mem_ctx, const struct brw_vs_prog_key *key, struct brw_vs_prog_data *prog_data, - nir_shader *shader, + nir_shader *nir, int shader_time_index, struct brw_compile_stats *stats, char **error_str) { const bool is_scalar = compiler->scalar_stage[MESA_SHADER_VERTEX]; - brw_nir_apply_key(shader, compiler, &key->base, 8, is_scalar); + brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar); const unsigned *assembly = NULL; @@ -2876,28 +2875,28 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data, */ assert(!is_scalar); assert(key->copy_edgeflag); - shader->info.inputs_read |= VERT_BIT_EDGEFLAG; + nir->info.inputs_read |= VERT_BIT_EDGEFLAG; } - prog_data->inputs_read = shader->info.inputs_read; - prog_data->double_inputs_read = shader->info.vs.double_inputs; + prog_data->inputs_read = nir->info.inputs_read; + prog_data->double_inputs_read = nir->info.vs.double_inputs; - brw_nir_lower_vs_inputs(shader, key->gl_attrib_wa_flags); - brw_nir_lower_vue_outputs(shader); - brw_postprocess_nir(shader, compiler, is_scalar); + brw_nir_lower_vs_inputs(nir, key->gl_attrib_wa_flags); + brw_nir_lower_vue_outputs(nir); + brw_postprocess_nir(nir, compiler, is_scalar); prog_data->base.clip_distance_mask = - ((1 << shader->info.clip_distance_array_size) - 1); + ((1 << nir->info.clip_distance_array_size) - 1); prog_data->base.cull_distance_mask = - ((1 << shader->info.cull_distance_array_size) - 1) << - shader->info.clip_distance_array_size; + ((1 << nir->info.cull_distance_array_size) - 1) << + nir->info.clip_distance_array_size; unsigned nr_attribute_slots = util_bitcount64(prog_data->inputs_read); /* gl_VertexID and gl_InstanceID are system values, but arrive via an * incoming vertex attribute. So, add an extra slot. */ - if (shader->info.system_values_read & + if (nir->info.system_values_read & (BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) | BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) | BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) | @@ -2906,33 +2905,33 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data, } /* gl_DrawID and IsIndexedDraw share its very own vec4 */ - if (shader->info.system_values_read & + if (nir->info.system_values_read & (BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID) | BITFIELD64_BIT(SYSTEM_VALUE_IS_INDEXED_DRAW))) { nr_attribute_slots++; } - if (shader->info.system_values_read & + if (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_IS_INDEXED_DRAW)) prog_data->uses_is_indexed_draw = true; - if (shader->info.system_values_read & + if (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX)) prog_data->uses_firstvertex = true; - if (shader->info.system_values_read & + if (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE)) prog_data->uses_baseinstance = true; - if (shader->info.system_values_read & + if (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE)) prog_data->uses_vertexid = true; - if (shader->info.system_values_read & + if (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID)) prog_data->uses_instanceid = true; - if (shader->info.system_values_read & + if (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID)) prog_data->uses_drawid = true; @@ -2978,7 +2977,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data, fs_visitor v(compiler, log_data, mem_ctx, &key->base, &prog_data->base.base, - shader, 8, shader_time_index); + nir, 8, shader_time_index); if (!v.run_vs()) { if (error_str) *error_str = ralloc_strdup(mem_ctx, v.fail_msg); @@ -2989,18 +2988,20 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data, prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs; fs_generator g(compiler, log_data, mem_ctx, - &prog_data->base.base, v.shader_stats, - v.runtime_check_aads_emit, MESA_SHADER_VERTEX); + &prog_data->base.base, v.runtime_check_aads_emit, + MESA_SHADER_VERTEX); if (INTEL_DEBUG & DEBUG_VS) { const char *debug_name = ralloc_asprintf(mem_ctx, "%s vertex shader %s", - shader->info.label ? shader->info.label : + nir->info.label ? nir->info.label : "unnamed", - shader->info.name); + nir->info.name); g.enable_debug(debug_name); } - g.generate_code(v.cfg, 8, stats); + g.generate_code(v.cfg, 8, v.shader_stats, + v.performance_analysis.require(), stats); + g.add_const_data(nir->constant_data, nir->constant_data_size); assembly = g.get_assembly(); } @@ -3008,7 +3009,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data, prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT; vec4_vs_visitor v(compiler, log_data, key, prog_data, - shader, mem_ctx, shader_time_index); + nir, mem_ctx, shader_time_index); if (!v.run()) { if (error_str) *error_str = ralloc_strdup(mem_ctx, v.fail_msg); @@ -3017,8 +3018,10 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data, } assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, - shader, &prog_data->base, - v.cfg, stats); + nir, &prog_data->base, + v.cfg, + v.performance_analysis.require(), + stats); } return assembly;