X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fintel%2Fdev%2Fgen_device_info.c;h=7a22476916bf1b26b59131f5a5ae37ca1952804d;hb=4aa7af9e9a4c19e10afaf4a3c756e62cf4d352c3;hp=79ec4e0262d1348b147c5a321e5224142a04a1ad;hpb=96e1c945f2bc4047a603753ae10fc4f27754361c;p=mesa.git diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c index 79ec4e0262d..7a22476916b 100644 --- a/src/intel/dev/gen_device_info.c +++ b/src/intel/dev/gen_device_info.c @@ -66,6 +66,9 @@ gen_device_name_to_pci_device_id(const char *name) { "cml", 0x9b41 }, { "cnl", 0x5a52 }, { "icl", 0x8a52 }, + { "ehl", 0x4500 }, + { "jsl", 0x4E71 }, + { "tgl", 0x9a49 }, }; for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) { @@ -82,8 +85,8 @@ gen_device_name_to_pci_device_id(const char *name) * * Returns -1 if the override is not set. */ -int -gen_get_pci_device_id_override(void) +static int +get_pci_device_id_override(void) { if (geteuid() == getuid()) { const char *devid_override = getenv("INTEL_DEVID_OVERRIDE"); @@ -216,7 +219,7 @@ static const struct gen_device_info gen_device_info_snb_gt2 = { .must_use_separate_stencil = true, \ .has_llc = true, \ .has_pln = true, \ - .has_64bit_types = true, \ + .has_64bit_float = true, \ .has_surface_tile_offset = true, \ .timestamp_frequency = 12500000 @@ -414,7 +417,8 @@ static const struct gen_device_info gen_device_info_hsw_gt3 = { .has_sample_with_hiz = false, \ .has_pln = true, \ .has_integer_dword_mul = true, \ - .has_64bit_types = true, \ + .has_64bit_float = true, \ + .has_64bit_int = true, \ .supports_simd16_3src = true, \ .has_surface_tile_offset = true, \ .num_thread_per_eu = 7, \ @@ -443,7 +447,8 @@ static const struct gen_device_info gen_device_info_bdw_gt1 = { [MESA_SHADER_VERTEX] = 2560, [MESA_SHADER_TESS_CTRL] = 504, [MESA_SHADER_TESS_EVAL] = 1536, - [MESA_SHADER_GEOMETRY] = 960, + /* Reduced from 960, seems to be similar to the bug on Gen9 GT1. */ + [MESA_SHADER_GEOMETRY] = 690, }, }, .simulator_id = 11, @@ -850,28 +855,28 @@ static const struct gen_device_info gen_device_info_cfl_gt3 = { .num_eu_per_subslice = 8, \ .l3_banks = _l3 -static const struct gen_device_info gen_device_info_cnl_2x8 = { +static const struct gen_device_info gen_device_info_cnl_gt0_5 = { /* GT0.5 */ GEN10_FEATURES(1, 1, subslices(2), 2), .is_cannonlake = true, .simulator_id = 15, }; -static const struct gen_device_info gen_device_info_cnl_3x8 = { +static const struct gen_device_info gen_device_info_cnl_gt1 = { /* GT1 */ GEN10_FEATURES(1, 1, subslices(3), 3), .is_cannonlake = true, .simulator_id = 15, }; -static const struct gen_device_info gen_device_info_cnl_4x8 = { +static const struct gen_device_info gen_device_info_cnl_gt1_5 = { /* GT 1.5 */ GEN10_FEATURES(1, 2, subslices(2, 2), 6), .is_cannonlake = true, .simulator_id = 15, }; -static const struct gen_device_info gen_device_info_cnl_5x8 = { +static const struct gen_device_info gen_device_info_cnl_gt2 = { /* GT2 */ GEN10_FEATURES(2, 2, subslices(3, 2), 6), .is_cannonlake = true, @@ -890,7 +895,8 @@ static const struct gen_device_info gen_device_info_cnl_5x8 = { #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \ GEN8_FEATURES, \ GEN11_HW_INFO, \ - .has_64bit_types = false, \ + .has_64bit_float = false, \ + .has_64bit_int = false, \ .has_integer_dword_mul = false, \ .has_sample_with_hiz = false, \ .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \ @@ -909,7 +915,7 @@ static const struct gen_device_info gen_device_info_cnl_5x8 = { [MESA_SHADER_GEOMETRY] = 1032, \ } -static const struct gen_device_info gen_device_info_icl_8x8 = { +static const struct gen_device_info gen_device_info_icl_gt2 = { GEN11_FEATURES(2, 1, subslices(8), 8), .urb = { .size = 1024, @@ -918,7 +924,7 @@ static const struct gen_device_info gen_device_info_icl_8x8 = { .simulator_id = 19, }; -static const struct gen_device_info gen_device_info_icl_6x8 = { +static const struct gen_device_info gen_device_info_icl_gt1_5 = { GEN11_FEATURES(1, 1, subslices(6), 6), .urb = { .size = 768, @@ -927,7 +933,7 @@ static const struct gen_device_info gen_device_info_icl_6x8 = { .simulator_id = 19, }; -static const struct gen_device_info gen_device_info_icl_4x8 = { +static const struct gen_device_info gen_device_info_icl_gt1 = { GEN11_FEATURES(1, 1, subslices(4), 6), .urb = { .size = 768, @@ -936,7 +942,7 @@ static const struct gen_device_info gen_device_info_icl_4x8 = { .simulator_id = 19, }; -static const struct gen_device_info gen_device_info_icl_1x8 = { +static const struct gen_device_info gen_device_info_icl_gt0_5 = { GEN11_FEATURES(1, 1, subslices(1), 6), .urb = { .size = 768, @@ -945,8 +951,9 @@ static const struct gen_device_info gen_device_info_icl_1x8 = { .simulator_id = 19, }; -static const struct gen_device_info gen_device_info_ehl_4x8 = { +static const struct gen_device_info gen_device_info_ehl_7 = { GEN11_FEATURES(1, 1, subslices(4), 4), + .is_elkhartlake = true, .urb = { .size = 512, .min_entries = { @@ -964,10 +971,30 @@ static const struct gen_device_info gen_device_info_ehl_4x8 = { .simulator_id = 28, }; -/* FIXME: Verfiy below entries when more information is available for this SKU. - */ -static const struct gen_device_info gen_device_info_ehl_4x4 = { +static const struct gen_device_info gen_device_info_ehl_6 = { + GEN11_FEATURES(1, 1, subslices(4), 4), + .is_elkhartlake = true, + .urb = { + .size = 512, + .min_entries = { + [MESA_SHADER_VERTEX] = 64, + [MESA_SHADER_TESS_EVAL] = 34, + }, + .max_entries = { + [MESA_SHADER_VERTEX] = 2384, + [MESA_SHADER_TESS_CTRL] = 1032, + [MESA_SHADER_TESS_EVAL] = 2384, + [MESA_SHADER_GEOMETRY] = 1032, + }, + }, + .disable_ccs_repack = true, + .num_eu_per_subslice = 6, + .simulator_id = 28, +}; + +static const struct gen_device_info gen_device_info_ehl_5 = { GEN11_FEATURES(1, 1, subslices(4), 4), + .is_elkhartlake = true, .urb = { .size = 512, .min_entries = { @@ -986,10 +1013,9 @@ static const struct gen_device_info gen_device_info_ehl_4x4 = { .simulator_id = 28, }; -/* FIXME: Verfiy below entries when more information is available for this SKU. - */ -static const struct gen_device_info gen_device_info_ehl_2x4 = { +static const struct gen_device_info gen_device_info_ehl_4 = { GEN11_FEATURES(1, 1, subslices(2), 4), + .is_elkhartlake = true, .urb = { .size = 512, .min_entries = { @@ -1008,6 +1034,54 @@ static const struct gen_device_info gen_device_info_ehl_2x4 = { .simulator_id = 28, }; +#define GEN12_URB_MIN_MAX_ENTRIES \ + .min_entries = { \ + [MESA_SHADER_VERTEX] = 64, \ + [MESA_SHADER_TESS_EVAL] = 34, \ + }, \ + .max_entries = { \ + [MESA_SHADER_VERTEX] = 3576, \ + [MESA_SHADER_TESS_CTRL] = 1548, \ + [MESA_SHADER_TESS_EVAL] = 3576, \ + [MESA_SHADER_GEOMETRY] = 1548, \ + } + +#define GEN12_HW_INFO \ + .gen = 12, \ + .has_pln = false, \ + .has_sample_with_hiz = false, \ + .has_aux_map = true, \ + .max_vs_threads = 546, \ + .max_gs_threads = 336, \ + .max_tcs_threads = 336, \ + .max_tes_threads = 546, \ + .max_cs_threads = 112, /* threads per DSS */ \ + .urb = { \ + GEN12_URB_MIN_MAX_ENTRIES, \ + } + +#define GEN12_FEATURES(_gt, _slices, _dual_subslices, _l3) \ + GEN8_FEATURES, \ + GEN12_HW_INFO, \ + .has_64bit_float = false, \ + .has_64bit_int = false, \ + .has_integer_dword_mul = false, \ + .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \ + .simulator_id = 22, \ + .urb.size = (_gt) == 1 ? 512 : 1024, \ + .num_subslices = _dual_subslices, \ + .num_eu_per_subslice = 16 + +#define dual_subslices(args...) { args, } + +static const struct gen_device_info gen_device_info_tgl_gt1 = { + GEN12_FEATURES(1, 1, dual_subslices(2), 8), +}; + +static const struct gen_device_info gen_device_info_tgl_gt2 = { + GEN12_FEATURES(2, 1, dual_subslices(6), 8), +}; + static void gen_device_info_set_eu_mask(struct gen_device_info *devinfo, unsigned slice, @@ -1059,68 +1133,6 @@ fill_masks(struct gen_device_info *devinfo) } } -bool -gen_device_info_update_from_masks(struct gen_device_info *devinfo, - uint32_t slice_mask, - uint32_t subslice_mask, - uint32_t n_eus) -{ - struct drm_i915_query_topology_info *topology; - - assert((slice_mask & 0xff) == slice_mask); - - size_t data_length = 100; - - topology = calloc(1, sizeof(*topology) + data_length); - if (!topology) - return false; - - topology->max_slices = util_last_bit(slice_mask); - topology->max_subslices = util_last_bit(subslice_mask); - - topology->subslice_offset = DIV_ROUND_UP(topology->max_slices, 8); - topology->subslice_stride = DIV_ROUND_UP(topology->max_subslices, 8); - - uint32_t n_subslices = __builtin_popcount(slice_mask) * - __builtin_popcount(subslice_mask); - uint32_t num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices); - uint32_t eu_mask = (1U << num_eu_per_subslice) - 1; - - topology->eu_offset = topology->subslice_offset + - DIV_ROUND_UP(topology->max_subslices, 8); - topology->eu_stride = DIV_ROUND_UP(num_eu_per_subslice, 8); - - /* Set slice mask in topology */ - for (int b = 0; b < topology->subslice_offset; b++) - topology->data[b] = (slice_mask >> (b * 8)) & 0xff; - - for (int s = 0; s < topology->max_slices; s++) { - - /* Set subslice mask in topology */ - for (int b = 0; b < topology->subslice_stride; b++) { - int subslice_offset = topology->subslice_offset + - s * topology->subslice_stride + b; - - topology->data[subslice_offset] = (subslice_mask >> (b * 8)) & 0xff; - } - - /* Set eu mask in topology */ - for (int ss = 0; ss < topology->max_subslices; ss++) { - for (int b = 0; b < topology->eu_stride; b++) { - int eu_offset = topology->eu_offset + - (s * topology->max_subslices + ss) * topology->eu_stride + b; - - topology->data[eu_offset] = (eu_mask >> (b * 8)) & 0xff; - } - } - } - - gen_device_info_update_from_topology(devinfo, topology); - free(topology); - - return true; -} - static void reset_masks(struct gen_device_info *devinfo) { @@ -1135,11 +1147,12 @@ reset_masks(struct gen_device_info *devinfo) memset(&devinfo->slice_masks, 0, sizeof(devinfo->slice_masks)); memset(devinfo->subslice_masks, 0, sizeof(devinfo->subslice_masks)); memset(devinfo->eu_masks, 0, sizeof(devinfo->eu_masks)); + memset(devinfo->ppipe_subslices, 0, sizeof(devinfo->ppipe_subslices)); } -void -gen_device_info_update_from_topology(struct gen_device_info *devinfo, - const struct drm_i915_query_topology_info *topology) +static void +update_from_topology(struct gen_device_info *devinfo, + const struct drm_i915_query_topology_info *topology) { reset_masks(devinfo); @@ -1160,17 +1173,34 @@ gen_device_info_update_from_topology(struct gen_device_info *devinfo, uint32_t n_subslices = 0; for (int s = 0; s < topology->max_slices; s++) { - if ((devinfo->slice_masks & (1UL << s)) == 0) + if ((devinfo->slice_masks & (1 << s)) == 0) continue; for (int b = 0; b < devinfo->subslice_slice_stride; b++) { devinfo->num_subslices[s] += - __builtin_popcount(devinfo->subslice_masks[b]); + __builtin_popcount(devinfo->subslice_masks[s * devinfo->subslice_slice_stride + b]); } n_subslices += devinfo->num_subslices[s]; } assert(n_subslices > 0); + if (devinfo->gen == 11) { + /* On ICL we only have one slice */ + assert(devinfo->slice_masks == 1); + + /* Count the number of subslices on each pixel pipe. Assume that + * subslices 0-3 are on pixel pipe 0, and 4-7 are on pixel pipe 1. + */ + unsigned subslices = devinfo->subslice_masks[0]; + unsigned ss = 0; + while (subslices > 0) { + if (subslices & 1) + devinfo->ppipe_subslices[ss >= 4 ? 1 : 0] += 1; + subslices >>= 1; + ss++; + } + } + uint32_t eu_mask_len = topology->eu_stride * topology->max_subslices * topology->max_slices; assert(sizeof(devinfo->eu_masks) >= eu_mask_len); @@ -1183,6 +1213,66 @@ gen_device_info_update_from_topology(struct gen_device_info *devinfo, devinfo->num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices); } +static bool +update_from_masks(struct gen_device_info *devinfo, uint32_t slice_mask, + uint32_t subslice_mask, uint32_t n_eus) +{ + struct drm_i915_query_topology_info *topology; + + assert((slice_mask & 0xff) == slice_mask); + + size_t data_length = 100; + + topology = calloc(1, sizeof(*topology) + data_length); + if (!topology) + return false; + + topology->max_slices = util_last_bit(slice_mask); + topology->max_subslices = util_last_bit(subslice_mask); + + topology->subslice_offset = DIV_ROUND_UP(topology->max_slices, 8); + topology->subslice_stride = DIV_ROUND_UP(topology->max_subslices, 8); + + uint32_t n_subslices = __builtin_popcount(slice_mask) * + __builtin_popcount(subslice_mask); + uint32_t num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices); + uint32_t eu_mask = (1U << num_eu_per_subslice) - 1; + + topology->eu_offset = topology->subslice_offset + + DIV_ROUND_UP(topology->max_subslices, 8); + topology->eu_stride = DIV_ROUND_UP(num_eu_per_subslice, 8); + + /* Set slice mask in topology */ + for (int b = 0; b < topology->subslice_offset; b++) + topology->data[b] = (slice_mask >> (b * 8)) & 0xff; + + for (int s = 0; s < topology->max_slices; s++) { + + /* Set subslice mask in topology */ + for (int b = 0; b < topology->subslice_stride; b++) { + int subslice_offset = topology->subslice_offset + + s * topology->subslice_stride + b; + + topology->data[subslice_offset] = (subslice_mask >> (b * 8)) & 0xff; + } + + /* Set eu mask in topology */ + for (int ss = 0; ss < topology->max_subslices; ss++) { + for (int b = 0; b < topology->eu_stride; b++) { + int eu_offset = topology->eu_offset + + (s * topology->max_subslices + ss) * topology->eu_stride + b; + + topology->data[eu_offset] = (eu_mask >> (b * 8)) & 0xff; + } + } + } + + update_from_topology(devinfo, topology); + free(topology); + + return true; +} + static bool getparam(int fd, uint32_t param, int *value) { @@ -1202,15 +1292,17 @@ getparam(int fd, uint32_t param, int *value) } bool -gen_get_device_info(int devid, struct gen_device_info *devinfo) +gen_get_device_info_from_pci_id(int pci_id, + struct gen_device_info *devinfo) { - switch (devid) { + switch (pci_id) { #undef CHIPSET -#define CHIPSET(id, family, name) \ +#define CHIPSET(id, family, fam_str, name) \ case id: *devinfo = gen_device_info_##family; break; #include "pci_ids/i965_pci_ids.h" +#include "pci_ids/iris_pci_ids.h" default: - fprintf(stderr, "Driver does not support the 0x%x PCI ID.\n", devid); + fprintf(stderr, "Driver does not support the 0x%x PCI ID.\n", pci_id); return false; } @@ -1238,17 +1330,19 @@ gen_get_device_info(int devid, struct gen_device_info *devinfo) * 4; /* effective subslices per slice */ break; case 11: + case 12: devinfo->max_wm_threads = 128 /* threads-per-PSD */ * devinfo->num_slices * 8; /* subslices per slice */ break; default: + assert(devinfo->gen < 9); break; } assert(devinfo->num_slices <= ARRAY_SIZE(devinfo->num_subslices)); - devinfo->chipset_id = devid; + devinfo->chipset_id = pci_id; return true; } @@ -1257,8 +1351,9 @@ gen_get_device_name(int devid) { switch (devid) { #undef CHIPSET -#define CHIPSET(id, family, name) case id: return name; +#define CHIPSET(id, family, fam_str, name) case id: return name " (" fam_str ")"; break; #include "pci_ids/i965_pci_ids.h" +#include "pci_ids/iris_pci_ids.h" default: return NULL; } @@ -1283,10 +1378,7 @@ getparam_topology(struct gen_device_info *devinfo, int fd) if (!getparam(fd, I915_PARAM_SUBSLICE_MASK, &subslice_mask)) return false; - return gen_device_info_update_from_masks(devinfo, - slice_mask, - subslice_mask, - n_eus); + return update_from_masks(devinfo, slice_mask, subslice_mask, n_eus); } /** @@ -1306,6 +1398,9 @@ query_topology(struct gen_device_info *devinfo, int fd) if (gen_ioctl(fd, DRM_IOCTL_I915_QUERY, &query)) return false; + if (item.length < 0) + return false; + struct drm_i915_query_topology_info *topo_info = (struct drm_i915_query_topology_info *) calloc(1, item.length); item.data_ptr = (uintptr_t) topo_info; @@ -1314,8 +1409,7 @@ query_topology(struct gen_device_info *devinfo, int fd) item.length <= 0) return false; - gen_device_info_update_from_topology(devinfo, - topo_info); + update_from_topology(devinfo, topo_info); free(topo_info); @@ -1326,16 +1420,16 @@ query_topology(struct gen_device_info *devinfo, int fd) bool gen_get_device_info_from_fd(int fd, struct gen_device_info *devinfo) { - int devid = gen_get_pci_device_id_override(); + int devid = get_pci_device_id_override(); if (devid > 0) { - if (!gen_get_device_info(devid, devinfo)) + if (!gen_get_device_info_from_pci_id(devid, devinfo)) return false; devinfo->no_hw = true; } else { /* query the device id */ if (!getparam(fd, I915_PARAM_CHIPSET_ID, &devid)) return false; - if (!gen_get_device_info(devid, devinfo)) + if (!gen_get_device_info_from_pci_id(devid, devinfo)) return false; devinfo->no_hw = false; } @@ -1353,7 +1447,7 @@ gen_get_device_info_from_fd(int fd, struct gen_device_info *devinfo) return false; if (!getparam(fd, I915_PARAM_REVISION, &devinfo->revision)) - return false; + devinfo->revision = 0; if (!query_topology(devinfo, fd)) { if (devinfo->gen >= 10) {