X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fintel%2Fisl%2Fisl.c;h=8e3d408bd3b57bd1d408c62f2084f7e840710d76;hb=959539fbbd1fc18fab85b23bb93e0716c170d010;hp=f0e948a1c9648eeef88aed1f26f528225c82f211;hpb=c1a70165be1e81204033c46dac1d8361366be236;p=mesa.git diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index f0e948a1c96..8e3d408bd3b 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -33,8 +33,55 @@ #include "isl_gen7.h" #include "isl_gen8.h" #include "isl_gen9.h" +#include "isl_gen12.h" #include "isl_priv.h" +void +isl_memcpy_linear_to_tiled(uint32_t xt1, uint32_t xt2, + uint32_t yt1, uint32_t yt2, + char *dst, const char *src, + uint32_t dst_pitch, int32_t src_pitch, + bool has_swizzling, + enum isl_tiling tiling, + isl_memcpy_type copy_type) +{ +#ifdef USE_SSE41 + if (copy_type == ISL_MEMCPY_STREAMING_LOAD) { + _isl_memcpy_linear_to_tiled_sse41( + xt1, xt2, yt1, yt2, dst, src, dst_pitch, src_pitch, has_swizzling, + tiling, copy_type); + return; + } +#endif + + _isl_memcpy_linear_to_tiled( + xt1, xt2, yt1, yt2, dst, src, dst_pitch, src_pitch, has_swizzling, + tiling, copy_type); +} + +void +isl_memcpy_tiled_to_linear(uint32_t xt1, uint32_t xt2, + uint32_t yt1, uint32_t yt2, + char *dst, const char *src, + int32_t dst_pitch, uint32_t src_pitch, + bool has_swizzling, + enum isl_tiling tiling, + isl_memcpy_type copy_type) +{ +#ifdef USE_SSE41 + if (copy_type == ISL_MEMCPY_STREAMING_LOAD) { + _isl_memcpy_tiled_to_linear_sse41( + xt1, xt2, yt1, yt2, dst, src, dst_pitch, src_pitch, has_swizzling, + tiling, copy_type); + return; + } +#endif + + _isl_memcpy_tiled_to_linear( + xt1, xt2, yt1, yt2, dst, src, dst_pitch, src_pitch, has_swizzling, + tiling, copy_type); +} + void PRINTFLIKE(3, 4) UNUSED __isl_finishme(const char *file, int line, const char *fmt, ...) { @@ -48,11 +95,73 @@ __isl_finishme(const char *file, int line, const char *fmt, ...) fprintf(stderr, "%s:%d: FINISHME: %s\n", file, line, buf); } +static void +isl_device_setup_mocs(struct isl_device *dev) +{ + if (dev->info->gen >= 12) { + if (dev->info->is_dg1) { + /* L3CC=WB */ + dev->mocs.internal = 5 << 1; + /* Displayables on DG1 are free to cache in L3 since L3 is transient + * and flushed at bottom of each submission. + */ + dev->mocs.external = 5 << 1; + } else { + /* TODO: Set PTE to MOCS 61 when the kernel is ready */ + /* TC=1/LLC Only, LeCC=1/Uncacheable, LRUM=0, L3CC=1/Uncacheable */ + dev->mocs.external = 3 << 1; + /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ + dev->mocs.internal = 2 << 1; + } + } else if (dev->info->gen >= 9) { + /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */ + dev->mocs.external = 1 << 1; + /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ + dev->mocs.internal = 2 << 1; + } else if (dev->info->gen >= 8) { + /* MEMORY_OBJECT_CONTROL_STATE: + * .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle, + * .TargetCache = L3DefertoPATforLLCeLLCselection, + * .AgeforQUADLRU = 0 + */ + dev->mocs.external = 0x18; + /* MEMORY_OBJECT_CONTROL_STATE: + * .MemoryTypeLLCeLLCCacheabilityControl = WB, + * .TargetCache = L3DefertoPATforLLCeLLCselection, + * .AgeforQUADLRU = 0 + */ + dev->mocs.internal = 0x78; + } else if (dev->info->gen >= 7) { + if (dev->info->is_haswell) { + /* MEMORY_OBJECT_CONTROL_STATE: + * .LLCeLLCCacheabilityControlLLCCC = 0, + * .L3CacheabilityControlL3CC = 1, + */ + dev->mocs.internal = 1; + dev->mocs.external = 1; + } else { + /* MEMORY_OBJECT_CONTROL_STATE: + * .GraphicsDataTypeGFDT = 0, + * .LLCCacheabilityControlLLCCC = 0, + * .L3CacheabilityControlL3CC = 1, + */ + dev->mocs.internal = 1; + dev->mocs.external = 1; + } + } else { + dev->mocs.internal = 0; + dev->mocs.external = 0; + } +} + void isl_device_init(struct isl_device *dev, const struct gen_device_info *info, bool has_bit6_swizzling) { + /* Gen8+ don't have bit6 swizzling, ensure callsite is not confused. */ + assert(!(has_bit6_swizzling && info->gen >= 8)); + dev->info = info; dev->use_separate_stencil = ISL_DEV_GEN(dev) >= 6; dev->has_bit6_swizzling = has_bit6_swizzling; @@ -73,6 +182,20 @@ isl_device_init(struct isl_device *dev, dev->ss.size = RENDER_SURFACE_STATE_length(info) * 4; dev->ss.align = isl_align(dev->ss.size, 32); + dev->ss.clear_color_state_size = + isl_align(CLEAR_COLOR_length(info) * 4, 64); + dev->ss.clear_color_state_offset = + RENDER_SURFACE_STATE_ClearValueAddress_start(info) / 32 * 4; + + dev->ss.clear_value_size = + isl_align(RENDER_SURFACE_STATE_RedClearColor_bits(info) + + RENDER_SURFACE_STATE_GreenClearColor_bits(info) + + RENDER_SURFACE_STATE_BlueClearColor_bits(info) + + RENDER_SURFACE_STATE_AlphaClearColor_bits(info), 32) / 8; + + dev->ss.clear_value_offset = + RENDER_SURFACE_STATE_RedClearColor_start(info) / 32 * 4; + assert(RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info) % 8 == 0); dev->ss.addr_offset = RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info) / 8; @@ -108,6 +231,12 @@ isl_device_init(struct isl_device *dev, dev->ds.stencil_offset = 0; dev->ds.hiz_offset = 0; } + + if (ISL_DEV_GEN(dev) >= 12) { + dev->ds.size += GEN12_MI_LOAD_REGISTER_IMM_length * 4 * 2; + } + + isl_device_setup_mocs(dev); } /** @@ -247,6 +376,29 @@ isl_tiling_get_info(enum isl_tiling tiling, phys_B = isl_extent2d(128, 32); break; + case ISL_TILING_GEN12_CCS: + /* From the Bspec, Gen Graphics > Gen12 > Memory Data Formats > Memory + * Compression > Memory Compression - Gen12: + * + * 4 bits of auxiliary plane data are required for 2 cachelines of + * main surface data. This results in a single cacheline of auxiliary + * plane data mapping to 4 4K pages of main surface data for the 4K + * pages (tile Y ) and 1 64K Tile Ys page. + * + * The Y-tiled pairing bit of 9 shown in the table below that Bspec + * section expresses that the 2 cachelines of main surface data are + * horizontally adjacent. + * + * TODO: Handle Ys, Yf and their pairing bits. + * + * Therefore, each CCS cacheline represents a 512Bx32 row area and each + * element represents a 32Bx4 row area. + */ + assert(format_bpb == 4); + logical_el = isl_extent2d(16, 8); + phys_B = isl_extent2d(64, 1); + break; + default: unreachable("not reached"); } /* end switch */ @@ -259,6 +411,53 @@ isl_tiling_get_info(enum isl_tiling tiling, }; } +bool +isl_color_value_is_zero(union isl_color_value value, + enum isl_format format) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(format); + +#define RETURN_FALSE_IF_NOT_0(c, i) \ + if (fmtl->channels.c.bits && value.u32[i] != 0) \ + return false + + RETURN_FALSE_IF_NOT_0(r, 0); + RETURN_FALSE_IF_NOT_0(g, 1); + RETURN_FALSE_IF_NOT_0(b, 2); + RETURN_FALSE_IF_NOT_0(a, 3); + +#undef RETURN_FALSE_IF_NOT_0 + + return true; +} + +bool +isl_color_value_is_zero_one(union isl_color_value value, + enum isl_format format) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(format); + +#define RETURN_FALSE_IF_NOT_0_1(c, i, field) \ + if (fmtl->channels.c.bits && value.field[i] != 0 && value.field[i] != 1) \ + return false + + if (isl_format_has_int_channel(format)) { + RETURN_FALSE_IF_NOT_0_1(r, 0, u32); + RETURN_FALSE_IF_NOT_0_1(g, 1, u32); + RETURN_FALSE_IF_NOT_0_1(b, 2, u32); + RETURN_FALSE_IF_NOT_0_1(a, 3, u32); + } else { + RETURN_FALSE_IF_NOT_0_1(r, 0, f32); + RETURN_FALSE_IF_NOT_0_1(g, 1, f32); + RETURN_FALSE_IF_NOT_0_1(b, 2, f32); + RETURN_FALSE_IF_NOT_0_1(a, 3, f32); + } + +#undef RETURN_FALSE_IF_NOT_0_1 + + return true; +} + /** * @param[out] tiling is set only on success */ @@ -273,15 +472,19 @@ isl_surf_choose_tiling(const struct isl_device *dev, if (info->usage & ISL_SURF_USAGE_HIZ_BIT) { assert(info->format == ISL_FORMAT_HIZ); assert(tiling_flags == ISL_TILING_HIZ_BIT); - *tiling = ISL_TILING_HIZ; + *tiling = isl_tiling_flag_to_enum(tiling_flags); return true; } /* CCS surfaces always use the CCS tiling */ if (info->usage & ISL_SURF_USAGE_CCS_BIT) { assert(isl_format_get_layout(info->format)->txc == ISL_TXC_CCS); - assert(tiling_flags == ISL_TILING_CCS_BIT); - *tiling = ISL_TILING_CCS; + UNUSED bool ivb_ccs = ISL_DEV_GEN(dev) < 12 && + tiling_flags == ISL_TILING_CCS_BIT; + UNUSED bool tgl_ccs = ISL_DEV_GEN(dev) >= 12 && + tiling_flags == ISL_TILING_GEN12_CCS_BIT; + assert(ivb_ccs != tgl_ccs); + *tiling = isl_tiling_flag_to_enum(tiling_flags); return true; } @@ -447,7 +650,6 @@ isl_choose_array_pitch_span(const struct isl_device *dev, * the storage for LODs other than LOD 0 is not needed. */ assert(info->levels == 1); - assert(phys_level0_sa->array_len == 1); return ISL_ARRAY_PITCH_SPAN_COMPACT; } else { if ((ISL_DEV_GEN(dev) == 5 || ISL_DEV_GEN(dev) == 6) && @@ -479,6 +681,12 @@ isl_choose_array_pitch_span(const struct isl_device *dev, * compact QPitch possible in order to conserve memory. */ return ISL_ARRAY_PITCH_SPAN_COMPACT; + + case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ: + /* Each array image in the gen6 stencil of HiZ surface is compact in the + * sense that every LOD is a compact array of the same size as LOD0. + */ + return ISL_ARRAY_PITCH_SPAN_COMPACT; } unreachable("bad isl_dim_layout"); @@ -510,14 +718,28 @@ isl_choose_image_alignment_el(const struct isl_device *dev, return; } else if (info->format == ISL_FORMAT_HIZ) { assert(ISL_DEV_GEN(dev) >= 6); - /* HiZ surfaces are always aligned to 16x8 pixels in the primary surface - * which works out to 2x2 HiZ elments. - */ - *image_align_el = isl_extent3d(2, 2, 1); + if (ISL_DEV_GEN(dev) == 6) { + /* HiZ surfaces on Sandy Bridge are packed tightly. */ + *image_align_el = isl_extent3d(1, 1, 1); + } else if (ISL_DEV_GEN(dev) < 12) { + /* On gen7+, HiZ surfaces are always aligned to 16x8 pixels in the + * primary surface which works out to 2x2 HiZ elments. + */ + *image_align_el = isl_extent3d(2, 2, 1); + } else { + /* On gen12+, HiZ surfaces are always aligned to 16x16 pixels in the + * primary surface which works out to 2x4 HiZ elments. + * TODO: Verify + */ + *image_align_el = isl_extent3d(2, 4, 1); + } return; } - if (ISL_DEV_GEN(dev) >= 9) { + if (ISL_DEV_GEN(dev) >= 12) { + isl_gen12_choose_image_alignment_el(dev, info, tiling, dim_layout, + msaa_layout, image_align_el); + } else if (ISL_DEV_GEN(dev) >= 9) { isl_gen9_choose_image_alignment_el(dev, info, tiling, dim_layout, msaa_layout, image_align_el); } else if (ISL_DEV_GEN(dev) >= 8) { @@ -538,8 +760,14 @@ isl_choose_image_alignment_el(const struct isl_device *dev, static enum isl_dim_layout isl_surf_choose_dim_layout(const struct isl_device *dev, enum isl_surf_dim logical_dim, - enum isl_tiling tiling) + enum isl_tiling tiling, + isl_surf_usage_flags_t usage) { + /* Sandy bridge needs a special layout for HiZ and stencil. */ + if (ISL_DEV_GEN(dev) == 6 && + (tiling == ISL_TILING_W || tiling == ISL_TILING_HIZ)) + return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ; + if (ISL_DEV_GEN(dev) >= 9) { switch (logical_dim) { case ISL_SURF_DIM_1D: @@ -569,6 +797,16 @@ isl_surf_choose_dim_layout(const struct isl_device *dev, switch (logical_dim) { case ISL_SURF_DIM_1D: case ISL_SURF_DIM_2D: + /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout": + * + * The cube face textures are stored in the same way as 3D surfaces + * are stored (see section 6.17.5 for details). For cube surfaces, + * however, the depth is equal to the number of faces (always 6) and + * is not reduced for each MIP. + */ + if (ISL_DEV_GEN(dev) == 4 && (usage & ISL_SURF_USAGE_CUBE_BIT)) + return ISL_DIM_LAYOUT_GEN4_3D; + return ISL_DIM_LAYOUT_GEN4_2D; case ISL_SURF_DIM_3D: return ISL_DIM_LAYOUT_GEN4_3D; @@ -581,7 +819,7 @@ isl_surf_choose_dim_layout(const struct isl_device *dev, /** * Calculate the physical extent of the surface's first level, in units of - * surface samples. The result is aligned to the format's compression block. + * surface samples. */ static void isl_calc_phys_level0_extent_sa(const struct isl_device *dev, @@ -593,8 +831,8 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev, { const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); - if (isl_format_is_yuv(info->format)) - isl_finishme("%s:%s: YUV format", __FILE__, __func__); + if (isl_format_is_planar(info->format)) + unreachable("Planar formats unsupported"); switch (info->dim) { case ISL_SURF_DIM_1D: @@ -608,9 +846,10 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev, case ISL_DIM_LAYOUT_GEN9_1D: case ISL_DIM_LAYOUT_GEN4_2D: + case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ: *phys_level0_sa = (struct isl_extent4d) { - .w = isl_align_npot(info->width, fmtl->bw), - .h = fmtl->bh, + .w = info->width, + .h = 1, .d = 1, .a = info->array_len, }; @@ -619,7 +858,11 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev, break; case ISL_SURF_DIM_2D: - assert(dim_layout == ISL_DIM_LAYOUT_GEN4_2D); + if (ISL_DEV_GEN(dev) == 4 && (info->usage & ISL_SURF_USAGE_CUBE_BIT)) + assert(dim_layout == ISL_DIM_LAYOUT_GEN4_3D); + else + assert(dim_layout == ISL_DIM_LAYOUT_GEN4_2D || + dim_layout == ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ); if (tiling == ISL_TILING_Ys && info->samples > 1) isl_finishme("%s:%s: multisample TileYs layout", __FILE__, __func__); @@ -630,8 +873,8 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev, assert(info->samples == 1); *phys_level0_sa = (struct isl_extent4d) { - .w = isl_align_npot(info->width, fmtl->bw), - .h = isl_align_npot(info->height, fmtl->bh), + .w = info->width, + .h = info->height, .d = 1, .a = info->array_len, }; @@ -666,9 +909,6 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev, isl_msaa_interleaved_scale_px_to_sa(info->samples, &phys_level0_sa->w, &phys_level0_sa->h); - - phys_level0_sa->w = isl_align(phys_level0_sa->w, fmtl->bw); - phys_level0_sa->h = isl_align(phys_level0_sa->h, fmtl->bh); break; } break; @@ -684,14 +924,15 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev, switch (dim_layout) { case ISL_DIM_LAYOUT_GEN9_1D: + case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ: unreachable("bad isl_dim_layout"); case ISL_DIM_LAYOUT_GEN4_2D: assert(ISL_DEV_GEN(dev) >= 9); *phys_level0_sa = (struct isl_extent4d) { - .w = isl_align_npot(info->width, fmtl->bw), - .h = isl_align_npot(info->height, fmtl->bh), + .w = info->width, + .h = info->height, .d = 1, .a = info->depth, }; @@ -700,8 +941,8 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev, case ISL_DIM_LAYOUT_GEN4_3D: assert(ISL_DEV_GEN(dev) < 9); *phys_level0_sa = (struct isl_extent4d) { - .w = isl_align(info->width, fmtl->bw), - .h = isl_align(info->height, fmtl->bh), + .w = info->width, + .h = info->height, .d = info->depth, .a = 1, }; @@ -711,6 +952,111 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev, } } +/** + * Calculate the pitch between physical array slices, in units of rows of + * surface elements. + */ +static uint32_t +isl_calc_array_pitch_el_rows_gen4_2d( + const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + const struct isl_tile_info *tile_info, + const struct isl_extent3d *image_align_sa, + const struct isl_extent4d *phys_level0_sa, + enum isl_array_pitch_span array_pitch_span, + const struct isl_extent2d *phys_slice0_sa) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + uint32_t pitch_sa_rows = 0; + + switch (array_pitch_span) { + case ISL_ARRAY_PITCH_SPAN_COMPACT: + pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h); + break; + case ISL_ARRAY_PITCH_SPAN_FULL: { + /* The QPitch equation is found in the Broadwell PRM >> Volume 5: + * Memory Views >> Common Surface Formats >> Surface Layout >> 2D + * Surfaces >> Surface Arrays. + */ + uint32_t H0_sa = phys_level0_sa->h; + uint32_t H1_sa = isl_minify(H0_sa, 1); + + uint32_t h0_sa = isl_align_npot(H0_sa, image_align_sa->h); + uint32_t h1_sa = isl_align_npot(H1_sa, image_align_sa->h); + + uint32_t m; + if (ISL_DEV_GEN(dev) >= 7) { + /* The QPitch equation changed slightly in Ivybridge. */ + m = 12; + } else { + m = 11; + } + + pitch_sa_rows = h0_sa + h1_sa + (m * image_align_sa->h); + + if (ISL_DEV_GEN(dev) == 6 && info->samples > 1 && + (info->height % 4 == 1)) { + /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1: + * Graphics Core >> Section 7.18.3.7: Surface Arrays: + * + * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than + * the value calculated in the equation above , for every + * other odd Surface Height starting from 1 i.e. 1,5,9,13. + * + * XXX(chadv): Is the errata natural corollary of the physical + * layout of interleaved samples? + */ + pitch_sa_rows += 4; + } + + pitch_sa_rows = isl_align_npot(pitch_sa_rows, fmtl->bh); + } /* end case */ + break; + } + + assert(pitch_sa_rows % fmtl->bh == 0); + uint32_t pitch_el_rows = pitch_sa_rows / fmtl->bh; + + if (ISL_DEV_GEN(dev) >= 9 && ISL_DEV_GEN(dev) <= 11 && + fmtl->txc == ISL_TXC_CCS) { + /* + * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632): + * + * "Mip-mapped and arrayed surfaces are supported with MCS buffer + * layout with these alignments in the RT space: Horizontal + * Alignment = 128 and Vertical Alignment = 64." + * + * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435): + * + * "For non-multisampled render target's CCS auxiliary surface, + * QPitch must be computed with Horizontal Alignment = 128 and + * Surface Vertical Alignment = 256. These alignments are only for + * CCS buffer and not for associated render target." + * + * The first restriction is already handled by isl_choose_image_alignment_el + * but the second restriction, which is an extension of the first, only + * applies to qpitch and must be applied here. + * + * The second restriction disappears on Gen12. + */ + assert(fmtl->bh == 4); + pitch_el_rows = isl_align(pitch_el_rows, 256 / 4); + } + + if (ISL_DEV_GEN(dev) >= 9 && + info->dim == ISL_SURF_DIM_3D && + tile_info->tiling != ISL_TILING_LINEAR) { + /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch: + * + * Tile Mode != Linear: This field must be set to an integer multiple + * of the tile height + */ + pitch_el_rows = isl_align(pitch_el_rows, tile_info->logical_extent_el.height); + } + + return pitch_el_rows; +} + /** * A variant of isl_calc_phys_slice0_extent_sa() specific to * ISL_DIM_LAYOUT_GEN4_2D. @@ -724,13 +1070,10 @@ isl_calc_phys_slice0_extent_sa_gen4_2d( const struct isl_extent4d *phys_level0_sa, struct isl_extent2d *phys_slice0_sa) { - const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); - assert(phys_level0_sa->depth == 1); if (info->levels == 1) { - /* Do not pad the surface to the image alignment. Instead, pad it only - * to the pixel format's block alignment. + /* Do not pad the surface to the image alignment. * * For tiled surfaces, using a reduced alignment here avoids wasting CPU * cycles on the below mipmap layout caluclations. Reducing the @@ -745,8 +1088,8 @@ isl_calc_phys_slice0_extent_sa_gen4_2d( * VkBufferImageCopy::bufferRowLength. */ *phys_slice0_sa = (struct isl_extent2d) { - .w = isl_align_npot(phys_level0_sa->w, fmtl->bw), - .h = isl_align_npot(phys_level0_sa->h, fmtl->bh), + .w = phys_level0_sa->w, + .h = phys_level0_sa->h, }; return; } @@ -787,43 +1130,158 @@ isl_calc_phys_slice0_extent_sa_gen4_2d( }; } +static void +isl_calc_phys_total_extent_el_gen4_2d( + const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + const struct isl_tile_info *tile_info, + enum isl_msaa_layout msaa_layout, + const struct isl_extent3d *image_align_sa, + const struct isl_extent4d *phys_level0_sa, + enum isl_array_pitch_span array_pitch_span, + uint32_t *array_pitch_el_rows, + struct isl_extent2d *total_extent_el) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + + struct isl_extent2d phys_slice0_sa; + isl_calc_phys_slice0_extent_sa_gen4_2d(dev, info, msaa_layout, + image_align_sa, phys_level0_sa, + &phys_slice0_sa); + *array_pitch_el_rows = + isl_calc_array_pitch_el_rows_gen4_2d(dev, info, tile_info, + image_align_sa, phys_level0_sa, + array_pitch_span, + &phys_slice0_sa); + *total_extent_el = (struct isl_extent2d) { + .w = isl_align_div_npot(phys_slice0_sa.w, fmtl->bw), + .h = *array_pitch_el_rows * (phys_level0_sa->array_len - 1) + + isl_align_div_npot(phys_slice0_sa.h, fmtl->bh), + }; +} + /** * A variant of isl_calc_phys_slice0_extent_sa() specific to * ISL_DIM_LAYOUT_GEN4_3D. */ static void -isl_calc_phys_slice0_extent_sa_gen4_3d( +isl_calc_phys_total_extent_el_gen4_3d( const struct isl_device *dev, const struct isl_surf_init_info *restrict info, const struct isl_extent3d *image_align_sa, const struct isl_extent4d *phys_level0_sa, - struct isl_extent2d *phys_slice0_sa) + uint32_t *array_pitch_el_rows, + struct isl_extent2d *phys_total_el) { + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + assert(info->samples == 1); - assert(phys_level0_sa->array_len == 1); - uint32_t slice_w = 0; - uint32_t slice_h = 0; + if (info->dim != ISL_SURF_DIM_3D) { + /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout": + * + * The cube face textures are stored in the same way as 3D surfaces + * are stored (see section 6.17.5 for details). For cube surfaces, + * however, the depth is equal to the number of faces (always 6) and + * is not reduced for each MIP. + */ + assert(ISL_DEV_GEN(dev) == 4); + assert(info->usage & ISL_SURF_USAGE_CUBE_BIT); + assert(phys_level0_sa->array_len == 6); + } else { + assert(phys_level0_sa->array_len == 1); + } + + uint32_t total_w = 0; + uint32_t total_h = 0; uint32_t W0 = phys_level0_sa->w; uint32_t H0 = phys_level0_sa->h; uint32_t D0 = phys_level0_sa->d; + uint32_t A0 = phys_level0_sa->a; for (uint32_t l = 0; l < info->levels; ++l) { uint32_t level_w = isl_align_npot(isl_minify(W0, l), image_align_sa->w); uint32_t level_h = isl_align_npot(isl_minify(H0, l), image_align_sa->h); - uint32_t level_d = isl_align_npot(isl_minify(D0, l), image_align_sa->d); + uint32_t level_d = info->dim == ISL_SURF_DIM_3D ? isl_minify(D0, l) : A0; uint32_t max_layers_horiz = MIN(level_d, 1u << l); uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l); - slice_w = MAX(slice_w, level_w * max_layers_horiz); - slice_h += level_h * max_layers_vert; + total_w = MAX(total_w, level_w * max_layers_horiz); + total_h += level_h * max_layers_vert; } - *phys_slice0_sa = (struct isl_extent2d) { - .w = slice_w, - .h = slice_h, + /* GEN4_3D layouts don't really have an array pitch since each LOD has a + * different number of horizontal and vertical layers. We have to set it + * to something, so at least make it true for LOD0. + */ + *array_pitch_el_rows = + isl_align_npot(phys_level0_sa->h, image_align_sa->h) / fmtl->bw; + *phys_total_el = (struct isl_extent2d) { + .w = isl_assert_div(total_w, fmtl->bw), + .h = isl_assert_div(total_h, fmtl->bh), + }; +} + +/** + * A variant of isl_calc_phys_slice0_extent_sa() specific to + * ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ. + */ +static void +isl_calc_phys_total_extent_el_gen6_stencil_hiz( + const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + const struct isl_tile_info *tile_info, + const struct isl_extent3d *image_align_sa, + const struct isl_extent4d *phys_level0_sa, + uint32_t *array_pitch_el_rows, + struct isl_extent2d *phys_total_el) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + + const struct isl_extent2d tile_extent_sa = { + .w = tile_info->logical_extent_el.w * fmtl->bw, + .h = tile_info->logical_extent_el.h * fmtl->bh, + }; + /* Tile size is a multiple of image alignment */ + assert(tile_extent_sa.w % image_align_sa->w == 0); + assert(tile_extent_sa.h % image_align_sa->h == 0); + + const uint32_t W0 = phys_level0_sa->w; + const uint32_t H0 = phys_level0_sa->h; + + /* Each image has the same height as LOD0 because the hardware thinks + * everything is LOD0 + */ + const uint32_t H = isl_align(H0, image_align_sa->h) * phys_level0_sa->a; + + uint32_t total_top_w = 0; + uint32_t total_bottom_w = 0; + uint32_t total_h = 0; + + for (uint32_t l = 0; l < info->levels; ++l) { + const uint32_t W = isl_minify(W0, l); + + const uint32_t w = isl_align(W, tile_extent_sa.w); + const uint32_t h = isl_align(H, tile_extent_sa.h); + + if (l == 0) { + total_top_w = w; + total_h = h; + } else if (l == 1) { + total_bottom_w = w; + total_h += h; + } else { + total_bottom_w += w; + } + } + + *array_pitch_el_rows = + isl_assert_div(isl_align(H0, image_align_sa->h), fmtl->bh); + *phys_total_el = (struct isl_extent2d) { + .w = isl_assert_div(MAX(total_top_w, total_bottom_w), fmtl->bw), + .h = isl_assert_div(total_h, fmtl->bh), }; } @@ -832,14 +1290,15 @@ isl_calc_phys_slice0_extent_sa_gen4_3d( * ISL_DIM_LAYOUT_GEN9_1D. */ static void -isl_calc_phys_slice0_extent_sa_gen9_1d( +isl_calc_phys_total_extent_el_gen9_1d( const struct isl_device *dev, const struct isl_surf_init_info *restrict info, const struct isl_extent3d *image_align_sa, const struct isl_extent4d *phys_level0_sa, - struct isl_extent2d *phys_slice0_sa) + uint32_t *array_pitch_el_rows, + struct isl_extent2d *phys_total_el) { - MAYBE_UNUSED const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); assert(phys_level0_sa->height == 1); assert(phys_level0_sa->depth == 1); @@ -856,164 +1315,90 @@ isl_calc_phys_slice0_extent_sa_gen9_1d( slice_w += w; } - *phys_slice0_sa = isl_extent2d(slice_w, 1); + *array_pitch_el_rows = 1; + *phys_total_el = (struct isl_extent2d) { + .w = isl_assert_div(slice_w, fmtl->bw), + .h = phys_level0_sa->array_len, + }; } /** - * Calculate the physical extent of the surface's first array slice, in units - * of surface samples. If the surface is multi-leveled, then the result will - * be aligned to \a image_align_sa. + * Calculate the two-dimensional total physical extent of the surface, in + * units of surface elements. */ static void -isl_calc_phys_slice0_extent_sa(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - enum isl_dim_layout dim_layout, - enum isl_msaa_layout msaa_layout, - const struct isl_extent3d *image_align_sa, - const struct isl_extent4d *phys_level0_sa, - struct isl_extent2d *phys_slice0_sa) +isl_calc_phys_total_extent_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + const struct isl_tile_info *tile_info, + enum isl_dim_layout dim_layout, + enum isl_msaa_layout msaa_layout, + const struct isl_extent3d *image_align_sa, + const struct isl_extent4d *phys_level0_sa, + enum isl_array_pitch_span array_pitch_span, + uint32_t *array_pitch_el_rows, + struct isl_extent2d *total_extent_el) { switch (dim_layout) { case ISL_DIM_LAYOUT_GEN9_1D: - isl_calc_phys_slice0_extent_sa_gen9_1d(dev, info, - image_align_sa, phys_level0_sa, - phys_slice0_sa); + assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT); + isl_calc_phys_total_extent_el_gen9_1d(dev, info, + image_align_sa, phys_level0_sa, + array_pitch_el_rows, + total_extent_el); return; case ISL_DIM_LAYOUT_GEN4_2D: - isl_calc_phys_slice0_extent_sa_gen4_2d(dev, info, msaa_layout, - image_align_sa, phys_level0_sa, - phys_slice0_sa); + isl_calc_phys_total_extent_el_gen4_2d(dev, info, tile_info, msaa_layout, + image_align_sa, phys_level0_sa, + array_pitch_span, + array_pitch_el_rows, + total_extent_el); + return; + case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ: + assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT); + isl_calc_phys_total_extent_el_gen6_stencil_hiz(dev, info, tile_info, + image_align_sa, + phys_level0_sa, + array_pitch_el_rows, + total_extent_el); return; case ISL_DIM_LAYOUT_GEN4_3D: - isl_calc_phys_slice0_extent_sa_gen4_3d(dev, info, image_align_sa, - phys_level0_sa, phys_slice0_sa); + assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT); + isl_calc_phys_total_extent_el_gen4_3d(dev, info, + image_align_sa, phys_level0_sa, + array_pitch_el_rows, + total_extent_el); return; } + + unreachable("invalid value for dim_layout"); } -/** - * Calculate the pitch between physical array slices, in units of rows of - * surface elements. - */ static uint32_t -isl_calc_array_pitch_el_rows(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - const struct isl_tile_info *tile_info, - enum isl_dim_layout dim_layout, - enum isl_array_pitch_span array_pitch_span, - const struct isl_extent3d *image_align_sa, - const struct isl_extent4d *phys_level0_sa, - const struct isl_extent2d *phys_slice0_sa) +isl_calc_row_pitch_alignment(const struct isl_device *dev, + const struct isl_surf_init_info *surf_info, + const struct isl_tile_info *tile_info) { - const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); - uint32_t pitch_sa_rows = 0; - - switch (dim_layout) { - case ISL_DIM_LAYOUT_GEN9_1D: - /* Each row is an array slice */ - pitch_sa_rows = 1; - break; - case ISL_DIM_LAYOUT_GEN4_2D: - switch (array_pitch_span) { - case ISL_ARRAY_PITCH_SPAN_COMPACT: - pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h); - break; - case ISL_ARRAY_PITCH_SPAN_FULL: { - /* The QPitch equation is found in the Broadwell PRM >> Volume 5: - * Memory Views >> Common Surface Formats >> Surface Layout >> 2D - * Surfaces >> Surface Arrays. - */ - uint32_t H0_sa = phys_level0_sa->h; - uint32_t H1_sa = isl_minify(H0_sa, 1); - - uint32_t h0_sa = isl_align_npot(H0_sa, image_align_sa->h); - uint32_t h1_sa = isl_align_npot(H1_sa, image_align_sa->h); - - uint32_t m; - if (ISL_DEV_GEN(dev) >= 7) { - /* The QPitch equation changed slightly in Ivybridge. */ - m = 12; - } else { - m = 11; - } + if (tile_info->tiling != ISL_TILING_LINEAR) { + /* According to BSpec: 44930, Gen12's CCS-compressed surface pitches must + * be 512B-aligned. CCS is only support on Y tilings. + * + * Only consider 512B alignment when : + * - AUX is not explicitly disabled + * - the caller has specified no pitch + * + * isl_surf_get_ccs_surf() will check that the main surface alignment + * matches CCS expectations. + */ + if (ISL_DEV_GEN(dev) >= 12 && + isl_format_supports_ccs_e(dev->info, surf_info->format) && + tile_info->tiling != ISL_TILING_X && + !(surf_info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT) && + surf_info->row_pitch_B == 0) { + return isl_align(tile_info->phys_extent_B.width, 512); + } - pitch_sa_rows = h0_sa + h1_sa + (m * image_align_sa->h); - - if (ISL_DEV_GEN(dev) == 6 && info->samples > 1 && - (info->height % 4 == 1)) { - /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1: - * Graphics Core >> Section 7.18.3.7: Surface Arrays: - * - * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than - * the value calculated in the equation above , for every - * other odd Surface Height starting from 1 i.e. 1,5,9,13. - * - * XXX(chadv): Is the errata natural corollary of the physical - * layout of interleaved samples? - */ - pitch_sa_rows += 4; - } - - pitch_sa_rows = isl_align_npot(pitch_sa_rows, fmtl->bh); - } /* end case */ - break; - } - break; - case ISL_DIM_LAYOUT_GEN4_3D: - assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT); - pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h); - break; - default: - unreachable("bad isl_dim_layout"); - break; - } - - assert(pitch_sa_rows % fmtl->bh == 0); - uint32_t pitch_el_rows = pitch_sa_rows / fmtl->bh; - - if (ISL_DEV_GEN(dev) >= 9 && fmtl->txc == ISL_TXC_CCS) { - /* - * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632): - * - * "Mip-mapped and arrayed surfaces are supported with MCS buffer - * layout with these alignments in the RT space: Horizontal - * Alignment = 128 and Vertical Alignment = 64." - * - * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435): - * - * "For non-multisampled render target's CCS auxiliary surface, - * QPitch must be computed with Horizontal Alignment = 128 and - * Surface Vertical Alignment = 256. These alignments are only for - * CCS buffer and not for associated render target." - * - * The first restriction is already handled by isl_choose_image_alignment_el - * but the second restriction, which is an extension of the first, only - * applies to qpitch and must be applied here. - */ - assert(fmtl->bh == 4); - pitch_el_rows = isl_align(pitch_el_rows, 256 / 4); - } - - if (ISL_DEV_GEN(dev) >= 9 && - info->dim == ISL_SURF_DIM_3D && - tile_info->tiling != ISL_TILING_LINEAR) { - /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch: - * - * Tile Mode != Linear: This field must be set to an integer multiple - * of the tile height - */ - pitch_el_rows = isl_align(pitch_el_rows, tile_info->logical_extent_el.height); - } - - return pitch_el_rows; -} - -static uint32_t -isl_calc_row_pitch_alignment(const struct isl_surf_init_info *surf_info, - const struct isl_tile_info *tile_info) -{ - if (tile_info->tiling != ISL_TILING_LINEAR) - return tile_info->phys_extent_B.width; + return tile_info->phys_extent_B.width; + } /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >> * RENDER_SURFACE_STATE Surface Pitch (p349): @@ -1031,67 +1416,78 @@ isl_calc_row_pitch_alignment(const struct isl_surf_init_info *surf_info, */ const struct isl_format_layout *fmtl = isl_format_get_layout(surf_info->format); const uint32_t bs = fmtl->bpb / 8; + uint32_t alignment; if (surf_info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) { if (isl_format_is_yuv(surf_info->format)) { - return 2 * bs; + alignment = 2 * bs; } else { - return bs; + alignment = bs; } + } else { + alignment = 1; } - return 1; + /* From the Broadwell PRM >> Volume 2c: Command Reference: Registers >> + * PRI_STRIDE Stride (p1254): + * + * "When using linear memory, this must be at least 64 byte aligned." + */ + if (surf_info->usage & ISL_SURF_USAGE_DISPLAY_BIT) + alignment = isl_align(alignment, 64); + + return alignment; } static uint32_t isl_calc_linear_min_row_pitch(const struct isl_device *dev, const struct isl_surf_init_info *info, - const struct isl_extent2d *phys_slice0_sa, - uint32_t alignment) + const struct isl_extent2d *phys_total_el, + uint32_t alignment_B) { const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); const uint32_t bs = fmtl->bpb / 8; - assert(phys_slice0_sa->w % fmtl->bw == 0); - - return isl_align_npot(bs * (phys_slice0_sa->w / fmtl->bw), alignment); + return isl_align_npot(bs * phys_total_el->w, alignment_B); } static uint32_t isl_calc_tiled_min_row_pitch(const struct isl_device *dev, const struct isl_surf_init_info *surf_info, const struct isl_tile_info *tile_info, - const struct isl_extent2d *phys_slice0_sa, - uint32_t alignment) + const struct isl_extent2d *phys_total_el, + uint32_t alignment_B) { const struct isl_format_layout *fmtl = isl_format_get_layout(surf_info->format); assert(fmtl->bpb % tile_info->format_bpb == 0); - assert(phys_slice0_sa->w % fmtl->bw == 0); const uint32_t tile_el_scale = fmtl->bpb / tile_info->format_bpb; - const uint32_t total_w_el = phys_slice0_sa->width / fmtl->bw; const uint32_t total_w_tl = - isl_align_div(total_w_el * tile_el_scale, + isl_align_div(phys_total_el->w * tile_el_scale, tile_info->logical_extent_el.width); - assert(alignment == tile_info->phys_extent_B.width); - return total_w_tl * tile_info->phys_extent_B.width; + /* In some cases the alignment of the pitch might be > to the tile size + * (for example Gen12 CCS requires 512B alignment while the tile's width + * can be 128B), so align the row pitch to the alignment. + */ + assert(alignment_B >= tile_info->phys_extent_B.width); + return isl_align(total_w_tl * tile_info->phys_extent_B.width, alignment_B); } static uint32_t isl_calc_min_row_pitch(const struct isl_device *dev, const struct isl_surf_init_info *surf_info, const struct isl_tile_info *tile_info, - const struct isl_extent2d *phys_slice0_sa, - uint32_t alignment) + const struct isl_extent2d *phys_total_el, + uint32_t alignment_B) { if (tile_info->tiling == ISL_TILING_LINEAR) { - return isl_calc_linear_min_row_pitch(dev, surf_info, phys_slice0_sa, - alignment); + return isl_calc_linear_min_row_pitch(dev, surf_info, phys_total_el, + alignment_B); } else { return isl_calc_tiled_min_row_pitch(dev, surf_info, tile_info, - phys_slice0_sa, alignment); + phys_total_el, alignment_B); } } @@ -1116,31 +1512,30 @@ isl_calc_row_pitch(const struct isl_device *dev, const struct isl_surf_init_info *surf_info, const struct isl_tile_info *tile_info, enum isl_dim_layout dim_layout, - const struct isl_extent2d *phys_slice0_sa, - uint32_t *out_row_pitch) + const struct isl_extent2d *phys_total_el, + uint32_t *out_row_pitch_B) { - const uint32_t alignment = - isl_calc_row_pitch_alignment(surf_info, tile_info); + uint32_t alignment_B = + isl_calc_row_pitch_alignment(dev, surf_info, tile_info); - const uint32_t min_row_pitch = - isl_calc_min_row_pitch(dev, surf_info, tile_info, phys_slice0_sa, - alignment); + const uint32_t min_row_pitch_B = + isl_calc_min_row_pitch(dev, surf_info, tile_info, phys_total_el, + alignment_B); - uint32_t row_pitch = min_row_pitch; - - if (surf_info->row_pitch != 0) { - row_pitch = surf_info->row_pitch; - - if (row_pitch < min_row_pitch) + if (surf_info->row_pitch_B != 0) { + if (surf_info->row_pitch_B < min_row_pitch_B) return false; - if (row_pitch % alignment != 0) + if (surf_info->row_pitch_B % alignment_B != 0) return false; } - const uint32_t row_pitch_tiles = row_pitch / tile_info->phys_extent_B.width; + const uint32_t row_pitch_B = + surf_info->row_pitch_B != 0 ? surf_info->row_pitch_B : min_row_pitch_B; + + const uint32_t row_pitch_tl = row_pitch_B / tile_info->phys_extent_B.width; - if (row_pitch == 0) + if (row_pitch_B == 0) return false; if (dim_layout == ISL_DIM_LAYOUT_GEN9_1D) { @@ -1151,140 +1546,35 @@ isl_calc_row_pitch(const struct isl_device *dev, if ((surf_info->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT | ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_STORAGE_BIT)) && - !pitch_in_range(row_pitch, RENDER_SURFACE_STATE_SurfacePitch_bits(dev->info))) + !pitch_in_range(row_pitch_B, RENDER_SURFACE_STATE_SurfacePitch_bits(dev->info))) return false; if ((surf_info->usage & (ISL_SURF_USAGE_CCS_BIT | ISL_SURF_USAGE_MCS_BIT)) && - !pitch_in_range(row_pitch_tiles, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev->info))) + !pitch_in_range(row_pitch_tl, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev->info))) return false; if ((surf_info->usage & ISL_SURF_USAGE_DEPTH_BIT) && - !pitch_in_range(row_pitch, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info))) + !pitch_in_range(row_pitch_B, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info))) return false; if ((surf_info->usage & ISL_SURF_USAGE_HIZ_BIT) && - !pitch_in_range(row_pitch, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev->info))) + !pitch_in_range(row_pitch_B, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev->info))) return false; - if (surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT) - isl_finishme("validate row pitch of stencil surfaces"); + const uint32_t stencil_pitch_bits = dev->use_separate_stencil ? + _3DSTATE_STENCIL_BUFFER_SurfacePitch_bits(dev->info) : + _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info); + + if ((surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT) && + !pitch_in_range(row_pitch_B, stencil_pitch_bits)) + return false; done: - *out_row_pitch = row_pitch; + *out_row_pitch_B = row_pitch_B; return true; } -/** - * Calculate and apply any padding required for the surface. - * - * @param[inout] total_h_el is updated with the new height - * @param[out] pad_bytes is overwritten with additional padding requirements. - */ -static void -isl_apply_surface_padding(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - const struct isl_tile_info *tile_info, - uint32_t *total_h_el, - uint32_t *pad_bytes) -{ - const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); - - *pad_bytes = 0; - - /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface - * Formats >> Surface Padding Requirements >> Render Target and Media - * Surfaces: - * - * The data port accesses data (pixels) outside of the surface if they - * are contained in the same cache request as pixels that are within the - * surface. These pixels will not be returned by the requesting message, - * however if these pixels lie outside of defined pages in the GTT, - * a GTT error will result when the cache request is processed. In - * order to avoid these GTT errors, “padding” at the bottom of the - * surface is sometimes necessary. - * - * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface - * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces: - * - * ... Lots of padding requirements, all listed separately below. - */ - - /* We can safely ignore the first padding requirement, quoted below, - * because isl doesn't do buffers. - * - * - [pre-BDW] For buffers, which have no inherent “height,” padding - * requirements are different. A buffer must be padded to the next - * multiple of 256 array elements, with an additional 16 bytes added - * beyond that to account for the L1 cache line. - */ - - /* - * - For compressed textures [...], padding at the bottom of the surface - * is to an even compressed row. - */ - if (isl_format_is_compressed(info->format)) - *total_h_el = isl_align(*total_h_el, 2); - - /* - * - For cube surfaces, an additional two rows of padding are required - * at the bottom of the surface. - */ - if (info->usage & ISL_SURF_USAGE_CUBE_BIT) - *total_h_el += 2; - - /* - * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats, - * additional padding is required. These surfaces require an extra row - * plus 16 bytes of padding at the bottom in addition to the general - * padding requirements. - */ - if (isl_format_is_yuv(info->format) && - (fmtl->bpb == 96 || fmtl->bpb == 48|| fmtl->bpb == 24)) { - *total_h_el += 1; - *pad_bytes += 16; - } - - /* - * - For linear surfaces, additional padding of 64 bytes is required at - * the bottom of the surface. This is in addition to the padding - * required above. - */ - if (tile_info->tiling == ISL_TILING_LINEAR) - *pad_bytes += 64; - - /* The below text weakens, not strengthens, the padding requirements for - * linear surfaces. Therefore we can safely ignore it. - * - * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array, - * non-MSAA, non-mip-mapped surfaces in linear memory, the only - * padding requirement is to the next aligned 64-byte boundary beyond - * the end of the surface. The rest of the padding requirements - * documented above do not apply to these surfaces. - */ - - /* - * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and - * height % 4 != 0, the surface must be padded with - * 4-(height % 4)*Surface Pitch # of bytes. - */ - if (ISL_DEV_GEN(dev) >= 9 && - tile_info->tiling == ISL_TILING_LINEAR && - (info->dim == ISL_SURF_DIM_2D || info->dim == ISL_SURF_DIM_3D)) { - *total_h_el = isl_align(*total_h_el, 4); - } - - /* - * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded - * to 4 times the Surface Pitch # of bytes - */ - if (ISL_DEV_GEN(dev) >= 9 && - tile_info->tiling == ISL_TILING_LINEAR && - info->dim == ISL_SURF_DIM_1D) { - *total_h_el += 4; - } -} - bool isl_surf_init_s(const struct isl_device *dev, struct isl_surf *surf, @@ -1307,7 +1597,7 @@ isl_surf_init_s(const struct isl_device *dev, isl_tiling_get_info(tiling, fmtl->bpb, &tile_info); const enum isl_dim_layout dim_layout = - isl_surf_choose_dim_layout(dev, info->dim, tiling); + isl_surf_choose_dim_layout(dev, info->dim, tiling, info->usage); enum isl_msaa_layout msaa_layout; if (!isl_choose_msaa_layout(dev, info, tiling, &msaa_layout)) @@ -1323,37 +1613,27 @@ isl_surf_init_s(const struct isl_device *dev, struct isl_extent4d phys_level0_sa; isl_calc_phys_level0_extent_sa(dev, info, dim_layout, tiling, msaa_layout, &phys_level0_sa); - assert(phys_level0_sa.w % fmtl->bw == 0); - assert(phys_level0_sa.h % fmtl->bh == 0); enum isl_array_pitch_span array_pitch_span = isl_choose_array_pitch_span(dev, info, dim_layout, &phys_level0_sa); - struct isl_extent2d phys_slice0_sa; - isl_calc_phys_slice0_extent_sa(dev, info, dim_layout, msaa_layout, - &image_align_sa, &phys_level0_sa, - &phys_slice0_sa); - assert(phys_slice0_sa.w % fmtl->bw == 0); - assert(phys_slice0_sa.h % fmtl->bh == 0); - - const uint32_t array_pitch_el_rows = - isl_calc_array_pitch_el_rows(dev, info, &tile_info, dim_layout, - array_pitch_span, &image_align_sa, - &phys_level0_sa, &phys_slice0_sa); - - uint32_t total_h_el = phys_level0_sa.array_len * array_pitch_el_rows; + uint32_t array_pitch_el_rows; + struct isl_extent2d phys_total_el; + isl_calc_phys_total_extent_el(dev, info, &tile_info, + dim_layout, msaa_layout, + &image_align_sa, &phys_level0_sa, + array_pitch_span, &array_pitch_el_rows, + &phys_total_el); - uint32_t pad_bytes; - isl_apply_surface_padding(dev, info, &tile_info, &total_h_el, &pad_bytes); - - uint32_t row_pitch; + uint32_t row_pitch_B; if (!isl_calc_row_pitch(dev, info, &tile_info, dim_layout, - &phys_slice0_sa, &row_pitch)) + &phys_total_el, &row_pitch_B)) return false; - uint32_t size, base_alignment; + uint32_t base_alignment_B; + uint64_t size_B; if (tiling == ISL_TILING_LINEAR) { - size = row_pitch * total_h_el + pad_bytes; + size_B = (uint64_t) row_pitch_B * phys_total_el.h; /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress: * @@ -1364,26 +1644,81 @@ isl_surf_init_s(const struct isl_device *dev, * surfaces have no alignment requirements (byte alignment is * sufficient.)" */ - base_alignment = MAX(1, info->min_alignment); + base_alignment_B = MAX(1, info->min_alignment_B); if (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) { if (isl_format_is_yuv(info->format)) { - base_alignment = MAX(base_alignment, fmtl->bpb / 4); + base_alignment_B = MAX(base_alignment_B, fmtl->bpb / 4); } else { - base_alignment = MAX(base_alignment, fmtl->bpb / 8); + base_alignment_B = MAX(base_alignment_B, fmtl->bpb / 8); } } - base_alignment = isl_round_up_to_power_of_two(base_alignment); + base_alignment_B = isl_round_up_to_power_of_two(base_alignment_B); + + /* From the Skylake PRM Vol 2c, PLANE_STRIDE::Stride: + * + * "For Linear memory, this field specifies the stride in chunks of + * 64 bytes (1 cache line)." + */ + if (isl_surf_usage_is_display(info->usage)) + base_alignment_B = MAX(base_alignment_B, 64); } else { - total_h_el += isl_align_div_npot(pad_bytes, row_pitch); const uint32_t total_h_tl = - isl_align_div(total_h_el, tile_info.logical_extent_el.height); + isl_align_div(phys_total_el.h, tile_info.logical_extent_el.height); + + size_B = (uint64_t) total_h_tl * tile_info.phys_extent_B.height * row_pitch_B; - size = total_h_tl * tile_info.phys_extent_B.height * row_pitch; + const uint32_t tile_size_B = tile_info.phys_extent_B.width * + tile_info.phys_extent_B.height; + assert(isl_is_pow2(info->min_alignment_B) && isl_is_pow2(tile_size_B)); + base_alignment_B = MAX(info->min_alignment_B, tile_size_B); - const uint32_t tile_size = tile_info.phys_extent_B.width * - tile_info.phys_extent_B.height; - assert(isl_is_pow2(info->min_alignment) && isl_is_pow2(tile_size)); - base_alignment = MAX(info->min_alignment, tile_size); + /* The diagram in the Bspec section Memory Compression - Gen12, shows + * that the CCS is indexed in 256B chunks. However, the + * PLANE_AUX_DIST::Auxiliary Surface Distance field is in units of 4K + * pages. We currently don't assign the usage field like we do for main + * surfaces, so just use 4K for now. + */ + if (tiling == ISL_TILING_GEN12_CCS) + base_alignment_B = MAX(base_alignment_B, 4096); + + /* Gen12+ requires that images be 64K-aligned if they're going to used + * with CCS. This is because the Aux translation table maps main + * surface addresses to aux addresses at a 64K (in the main surface) + * granularity. Because we don't know for sure in ISL if a surface will + * use CCS, we have to guess based on the DISABLE_AUX usage bit. The + * one thing we do know is that we haven't enable CCS on linear images + * yet so we can avoid the extra alignment there. + */ + if (ISL_DEV_GEN(dev) >= 12 && + !(info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)) { + base_alignment_B = MAX(base_alignment_B, 64 * 1024); + } + } + + if (ISL_DEV_GEN(dev) < 9) { + /* From the Broadwell PRM Vol 5, Surface Layout: + * + * "In addition to restrictions on maximum height, width, and depth, + * surfaces are also restricted to a maximum size in bytes. This + * maximum is 2 GB for all products and all surface types." + * + * This comment is applicable to all Pre-gen9 platforms. + */ + if (size_B > (uint64_t) 1 << 31) + return false; + } else if (ISL_DEV_GEN(dev) < 11) { + /* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes: + * "In addition to restrictions on maximum height, width, and depth, + * surfaces are also restricted to a maximum size of 2^38 bytes. + * All pixels within the surface must be contained within 2^38 bytes + * of the base address." + */ + if (size_B > (uint64_t) 1 << 38) + return false; + } else { + /* gen11+ platforms raised this limit to 2^44 bytes. */ + if (size_B > (uint64_t) 1 << 44) + return false; } *surf = (struct isl_surf) { @@ -1400,9 +1735,9 @@ isl_surf_init_s(const struct isl_device *dev, .logical_level0_px = logical_level0_px, .phys_level0_sa = phys_level0_sa, - .size = size, - .alignment = base_alignment, - .row_pitch = row_pitch, + .size_B = size_B, + .alignment_B = base_alignment_B, + .row_pitch_B = row_pitch_B, .array_pitch_el_rows = array_pitch_el_rows, .array_pitch_span = array_pitch_span, @@ -1427,6 +1762,34 @@ isl_surf_get_hiz_surf(const struct isl_device *dev, { assert(ISL_DEV_GEN(dev) >= 5 && ISL_DEV_USE_SEPARATE_STENCIL(dev)); + if (!isl_surf_usage_is_depth(surf->usage)) + return false; + + /* HiZ only works with Y-tiled depth buffers */ + if (!isl_tiling_is_any_y(surf->tiling)) + return false; + + /* On SNB+, compressed depth buffers cannot be interleaved with stencil. */ + switch (surf->format) { + case ISL_FORMAT_R24_UNORM_X8_TYPELESS: + if (isl_surf_usage_is_depth_and_stencil(surf->usage)) { + assert(ISL_DEV_GEN(dev) == 5); + unreachable("This should work, but is untested"); + } + /* Fall through */ + case ISL_FORMAT_R16_UNORM: + case ISL_FORMAT_R32_FLOAT: + break; + case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS: + if (ISL_DEV_GEN(dev) == 5) { + assert(isl_surf_usage_is_depth_and_stencil(surf->usage)); + unreachable("This should work, but is untested"); + } + /* Fall through */ + default: + return false; + } + /* Multisampled depth is always interleaved */ assert(surf->msaa_layout == ISL_MSAA_LAYOUT_NONE || surf->msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED); @@ -1507,13 +1870,32 @@ isl_surf_get_mcs_surf(const struct isl_device *dev, struct isl_surf *mcs_surf) { /* It must be multisampled with an array layout */ - assert(surf->samples > 1 && surf->msaa_layout == ISL_MSAA_LAYOUT_ARRAY); + if (surf->msaa_layout != ISL_MSAA_LAYOUT_ARRAY) + return false; + + if (mcs_surf->size_B > 0) + return false; /* The following are true of all multisampled surfaces */ + assert(surf->samples > 1); assert(surf->dim == ISL_SURF_DIM_2D); assert(surf->levels == 1); assert(surf->logical_level0_px.depth == 1); + /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"): + * + * This field must be set to 0 for all SINT MSRTs when all RT channels + * are not written + * + * In practice this means that we have to disable MCS for all signed + * integer MSAA buffers. The alternative, to disable MCS only when one + * of the render target channels is disabled, is impractical because it + * would require converting between CMS and UMS MSAA layouts on the fly, + * which is expensive. + */ + if (ISL_DEV_GEN(dev) == 7 && isl_format_has_sint_channel(surf->format)) + return false; + /* The "Auxiliary Surface Pitch" field in RENDER_SURFACE_STATE is only 9 * bits which means the maximum pitch of a compression surface is 512 * tiles or 64KB (since MCS is always Y-tiled). Since a 16x MCS buffer is @@ -1548,69 +1930,285 @@ isl_surf_get_mcs_surf(const struct isl_device *dev, } bool -isl_surf_get_ccs_surf(const struct isl_device *dev, - const struct isl_surf *surf, - struct isl_surf *ccs_surf) +isl_surf_supports_ccs(const struct isl_device *dev, + const struct isl_surf *surf) { - assert(surf->samples == 1 && surf->msaa_layout == ISL_MSAA_LAYOUT_NONE); - assert(ISL_DEV_GEN(dev) >= 7); + /* CCS support does not exist prior to Gen7 */ + if (ISL_DEV_GEN(dev) <= 6) + return false; if (surf->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT) return false; - if (ISL_DEV_GEN(dev) <= 8 && surf->dim != ISL_SURF_DIM_2D) + if (isl_format_is_compressed(surf->format)) return false; - if (isl_format_is_compressed(surf->format)) + if (!isl_is_pow2(isl_format_get_layout(surf->format)->bpb)) return false; - /* TODO: More conditions where it can fail. */ + /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render + * Target(s)", beneath the "Fast Color Clear" bullet (p326): + * + * - Support is limited to tiled render targets. + * + * From the Skylake documentation, it is made clear that X-tiling is no + * longer supported: + * + * - MCS and Lossless compression is supported for + * TiledY/TileYs/TileYf non-MSRTs only. + * + * From the BSpec (44930) for Gen12: + * + * Linear CCS is only allowed for Untyped Buffers but only via HDC + * Data-Port messages. + * + * We never use untyped messages on surfaces created by ISL on Gen9+ so + * this means linear is out on Gen12+ as well. + */ + if (surf->tiling == ISL_TILING_LINEAR) + return false; - enum isl_format ccs_format; - if (ISL_DEV_GEN(dev) >= 9) { - if (!isl_tiling_is_any_y(surf->tiling)) + if (ISL_DEV_GEN(dev) >= 12) { + if (isl_surf_usage_is_stencil(surf->usage) && surf->samples > 1) return false; - switch (isl_format_get_layout(surf->format)->bpb) { - case 32: ccs_format = ISL_FORMAT_GEN9_CCS_32BPP; break; - case 64: ccs_format = ISL_FORMAT_GEN9_CCS_64BPP; break; - case 128: ccs_format = ISL_FORMAT_GEN9_CCS_128BPP; break; - default: + /* On Gen12, 8BPP surfaces cannot be compressed if any level is not + * 32Bx4row-aligned. For now, just reject the cases where alignment + * matters. + */ + if (isl_format_get_layout(surf->format)->bpb == 8 && surf->levels >= 3) { + isl_finishme("%s:%s: CCS for 8BPP textures with 3+ miplevels is " + "disabled, but support for more levels is possible.", + __FILE__, __func__); return false; } - } else if (surf->tiling == ISL_TILING_Y0) { - switch (isl_format_get_layout(surf->format)->bpb) { - case 32: ccs_format = ISL_FORMAT_GEN7_CCS_32BPP_Y; break; - case 64: ccs_format = ISL_FORMAT_GEN7_CCS_64BPP_Y; break; - case 128: ccs_format = ISL_FORMAT_GEN7_CCS_128BPP_Y; break; - default: + + /* On Gen12, all CCS-compressed surface pitches must be multiples of + * 512B. + */ + if (surf->row_pitch_B % 512 != 0) + return false; + + /* According to GEN:BUG:1406738321, 3D textures need a blit to a new + * surface in order to perform a resolve. For now, just disable CCS. + */ + if (surf->dim == ISL_SURF_DIM_3D) { + isl_finishme("%s:%s: CCS for 3D textures is disabled, but a workaround" + " is available.", __FILE__, __func__); return false; } - } else if (surf->tiling == ISL_TILING_X) { + + /* GEN:BUG:1207137018 + * + * TODO: implement following workaround currently covered by the + * restriction above. If following conditions are met: + * + * - RENDER_SURFACE_STATE.Surface Type == 3D + * - RENDER_SURFACE_STATE.Auxiliary Surface Mode != AUX_NONE + * - RENDER_SURFACE_STATE.Tiled ResourceMode is TYF or TYS + * + * Set the value of RENDER_SURFACE_STATE.Mip Tail Start LOD to a mip + * that larger than those present in the surface (i.e. 15) + */ + + /* TODO: Handle the other tiling formats */ + if (surf->tiling != ISL_TILING_Y0) + return false; + } else { + /* ISL_DEV_GEN(dev) < 12 */ + if (surf->samples > 1) + return false; + + /* CCS is only for color images on Gen7-11 */ + if (isl_surf_usage_is_depth_or_stencil(surf->usage)) + return false; + + /* The PRM doesn't say this explicitly, but fast-clears don't appear to + * work for 3D textures until gen9 where the layout of 3D textures + * changes to match 2D array textures. + */ + if (ISL_DEV_GEN(dev) <= 8 && surf->dim != ISL_SURF_DIM_2D) + return false; + + /* From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652 (Color Clear of + * Non-MultiSampler Render Target Restrictions): + * + * "Support is for non-mip-mapped and non-array surface types only." + * + * This restriction is lifted on gen8+. Technically, it may be possible + * to create a CCS for an arrayed or mipmapped image and only enable + * CCS_D when rendering to the base slice. However, there is no + * documentation tell us what the hardware would do in that case or what + * it does if you walk off the bases slice. (Does it ignore CCS or does + * it start scribbling over random memory?) We play it safe and just + * follow the docs and don't allow CCS_D for arrayed or mip-mapped + * surfaces. + */ + if (ISL_DEV_GEN(dev) <= 7 && + (surf->levels > 1 || surf->logical_level0_px.array_len > 1)) + return false; + + /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render + * Target(s)", beneath the "Fast Color Clear" bullet (p326): + * + * - MCS buffer for non-MSRT is supported only for RT formats 32bpp, + * 64bpp, and 128bpp. + */ + if (isl_format_get_layout(surf->format)->bpb < 32) + return false; + + /* From the Skylake documentation, it is made clear that X-tiling is no + * longer supported: + * + * - MCS and Lossless compression is supported for + * TiledY/TileYs/TileYf non-MSRTs only. + */ + if (ISL_DEV_GEN(dev) >= 9 && !isl_tiling_is_any_y(surf->tiling)) + return false; + } + + return true; +} + +bool +isl_surf_get_ccs_surf(const struct isl_device *dev, + const struct isl_surf *surf, + struct isl_surf *aux_surf, + struct isl_surf *extra_aux_surf, + uint32_t row_pitch_B) +{ + assert(aux_surf); + + /* An uninitialized surface is needed to get a CCS surface. */ + if (aux_surf->size_B > 0 && + (extra_aux_surf == NULL || extra_aux_surf->size_B > 0)) { + return false; + } + + /* A surface can't have two CCS surfaces. */ + if (aux_surf->usage & ISL_SURF_USAGE_CCS_BIT) + return false; + + if (!isl_surf_supports_ccs(dev, surf)) + return false; + + if (ISL_DEV_GEN(dev) >= 12) { + enum isl_format ccs_format; switch (isl_format_get_layout(surf->format)->bpb) { - case 32: ccs_format = ISL_FORMAT_GEN7_CCS_32BPP_X; break; - case 64: ccs_format = ISL_FORMAT_GEN7_CCS_64BPP_X; break; - case 128: ccs_format = ISL_FORMAT_GEN7_CCS_128BPP_X; break; + case 8: ccs_format = ISL_FORMAT_GEN12_CCS_8BPP_Y0; break; + case 16: ccs_format = ISL_FORMAT_GEN12_CCS_16BPP_Y0; break; + case 32: ccs_format = ISL_FORMAT_GEN12_CCS_32BPP_Y0; break; + case 64: ccs_format = ISL_FORMAT_GEN12_CCS_64BPP_Y0; break; + case 128: ccs_format = ISL_FORMAT_GEN12_CCS_128BPP_Y0; break; default: return false; } + + /* On Gen12, the CCS is a scaled-down version of the main surface. We + * model this as the CCS compressing a 2D-view of the entire surface. + */ + struct isl_surf *ccs_surf = + aux_surf->size_B > 0 ? extra_aux_surf : aux_surf; + const bool ok = + isl_surf_init(dev, ccs_surf, + .dim = ISL_SURF_DIM_2D, + .format = ccs_format, + .width = isl_surf_get_row_pitch_el(surf), + .height = surf->size_B / surf->row_pitch_B, + .depth = 1, + .levels = 1, + .array_len = 1, + .samples = 1, + .row_pitch_B = row_pitch_B, + .usage = ISL_SURF_USAGE_CCS_BIT, + .tiling_flags = ISL_TILING_GEN12_CCS_BIT); + assert(!ok || ccs_surf->size_B == surf->size_B / 256); + return ok; } else { - return false; - } + enum isl_format ccs_format; + if (ISL_DEV_GEN(dev) >= 9) { + switch (isl_format_get_layout(surf->format)->bpb) { + case 32: ccs_format = ISL_FORMAT_GEN9_CCS_32BPP; break; + case 64: ccs_format = ISL_FORMAT_GEN9_CCS_64BPP; break; + case 128: ccs_format = ISL_FORMAT_GEN9_CCS_128BPP; break; + default: unreachable("Unsupported CCS format"); + return false; + } + } else if (surf->tiling == ISL_TILING_Y0) { + switch (isl_format_get_layout(surf->format)->bpb) { + case 32: ccs_format = ISL_FORMAT_GEN7_CCS_32BPP_Y; break; + case 64: ccs_format = ISL_FORMAT_GEN7_CCS_64BPP_Y; break; + case 128: ccs_format = ISL_FORMAT_GEN7_CCS_128BPP_Y; break; + default: unreachable("Unsupported CCS format"); + } + } else if (surf->tiling == ISL_TILING_X) { + switch (isl_format_get_layout(surf->format)->bpb) { + case 32: ccs_format = ISL_FORMAT_GEN7_CCS_32BPP_X; break; + case 64: ccs_format = ISL_FORMAT_GEN7_CCS_64BPP_X; break; + case 128: ccs_format = ISL_FORMAT_GEN7_CCS_128BPP_X; break; + default: unreachable("Unsupported CCS format"); + } + } else { + unreachable("Invalid tiling format"); + } - return isl_surf_init(dev, ccs_surf, - .dim = surf->dim, - .format = ccs_format, - .width = surf->logical_level0_px.width, - .height = surf->logical_level0_px.height, - .depth = surf->logical_level0_px.depth, - .levels = surf->levels, - .array_len = surf->logical_level0_px.array_len, - .samples = 1, - .usage = ISL_SURF_USAGE_CCS_BIT, - .tiling_flags = ISL_TILING_CCS_BIT); + return isl_surf_init(dev, aux_surf, + .dim = surf->dim, + .format = ccs_format, + .width = surf->logical_level0_px.width, + .height = surf->logical_level0_px.height, + .depth = surf->logical_level0_px.depth, + .levels = surf->levels, + .array_len = surf->logical_level0_px.array_len, + .samples = 1, + .row_pitch_B = row_pitch_B, + .usage = ISL_SURF_USAGE_CCS_BIT, + .tiling_flags = ISL_TILING_CCS_BIT); + } } +#define isl_genX_call(dev, func, ...) \ + switch (ISL_DEV_GEN(dev)) { \ + case 4: \ + /* G45 surface state is the same as gen5 */ \ + if (ISL_DEV_IS_G4X(dev)) { \ + isl_gen5_##func(__VA_ARGS__); \ + } else { \ + isl_gen4_##func(__VA_ARGS__); \ + } \ + break; \ + case 5: \ + isl_gen5_##func(__VA_ARGS__); \ + break; \ + case 6: \ + isl_gen6_##func(__VA_ARGS__); \ + break; \ + case 7: \ + if (ISL_DEV_IS_HASWELL(dev)) { \ + isl_gen75_##func(__VA_ARGS__); \ + } else { \ + isl_gen7_##func(__VA_ARGS__); \ + } \ + break; \ + case 8: \ + isl_gen8_##func(__VA_ARGS__); \ + break; \ + case 9: \ + isl_gen9_##func(__VA_ARGS__); \ + break; \ + case 10: \ + isl_gen10_##func(__VA_ARGS__); \ + break; \ + case 11: \ + isl_gen11_##func(__VA_ARGS__); \ + break; \ + case 12: \ + isl_gen12_##func(__VA_ARGS__); \ + break; \ + default: \ + assert(!"Unknown hardware generation"); \ + } + void isl_surf_fill_state_s(const struct isl_device *dev, void *state, const struct isl_surf_fill_state_info *restrict info) @@ -1634,68 +2232,21 @@ isl_surf_fill_state_s(const struct isl_device *dev, void *state, info->surf->logical_level0_px.array_len); } - switch (ISL_DEV_GEN(dev)) { - case 4: - if (ISL_DEV_IS_G4X(dev)) { - /* G45 surface state is the same as gen5 */ - isl_gen5_surf_fill_state_s(dev, state, info); - } else { - isl_gen4_surf_fill_state_s(dev, state, info); - } - break; - case 5: - isl_gen5_surf_fill_state_s(dev, state, info); - break; - case 6: - isl_gen6_surf_fill_state_s(dev, state, info); - break; - case 7: - if (ISL_DEV_IS_HASWELL(dev)) { - isl_gen75_surf_fill_state_s(dev, state, info); - } else { - isl_gen7_surf_fill_state_s(dev, state, info); - } - break; - case 8: - isl_gen8_surf_fill_state_s(dev, state, info); - break; - case 9: - isl_gen9_surf_fill_state_s(dev, state, info); - break; - default: - assert(!"Cannot fill surface state for this gen"); - } + isl_genX_call(dev, surf_fill_state_s, dev, state, info); } void isl_buffer_fill_state_s(const struct isl_device *dev, void *state, const struct isl_buffer_fill_state_info *restrict info) { - switch (ISL_DEV_GEN(dev)) { - case 4: - case 5: - /* Gen 4-5 are all the same when it comes to buffer surfaces */ - isl_gen5_buffer_fill_state_s(state, info); - break; - case 6: - isl_gen6_buffer_fill_state_s(state, info); - break; - case 7: - if (ISL_DEV_IS_HASWELL(dev)) { - isl_gen75_buffer_fill_state_s(state, info); - } else { - isl_gen7_buffer_fill_state_s(state, info); - } - break; - case 8: - isl_gen8_buffer_fill_state_s(state, info); - break; - case 9: - isl_gen9_buffer_fill_state_s(state, info); - break; - default: - assert(!"Cannot fill surface state for this gen"); - } + isl_genX_call(dev, buffer_fill_state_s, dev, state, info); +} + +void +isl_null_fill_state(const struct isl_device *dev, void *state, + struct isl_extent3d size) +{ + isl_genX_call(dev, null_fill_state, state, size); } void @@ -1732,37 +2283,7 @@ isl_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch, } } - switch (ISL_DEV_GEN(dev)) { - case 4: - if (ISL_DEV_IS_G4X(dev)) { - /* G45 surface state is the same as gen5 */ - isl_gen5_emit_depth_stencil_hiz_s(dev, batch, info); - } else { - isl_gen4_emit_depth_stencil_hiz_s(dev, batch, info); - } - break; - case 5: - isl_gen5_emit_depth_stencil_hiz_s(dev, batch, info); - break; - case 6: - isl_gen6_emit_depth_stencil_hiz_s(dev, batch, info); - break; - case 7: - if (ISL_DEV_IS_HASWELL(dev)) { - isl_gen75_emit_depth_stencil_hiz_s(dev, batch, info); - } else { - isl_gen7_emit_depth_stencil_hiz_s(dev, batch, info); - } - break; - case 8: - isl_gen8_emit_depth_stencil_hiz_s(dev, batch, info); - break; - case 9: - isl_gen9_emit_depth_stencil_hiz_s(dev, batch, info); - break; - default: - assert(!"Cannot fill surface state for this gen"); - } + isl_genX_call(dev, emit_depth_stencil_hiz_s, dev, batch, info); } /** @@ -1864,6 +2385,65 @@ get_image_offset_sa_gen4_3d(const struct isl_surf *surf, *y_offset_sa = y; } +static void +get_image_offset_sa_gen6_stencil_hiz(const struct isl_surf *surf, + uint32_t level, + uint32_t logical_array_layer, + uint32_t *x_offset_sa, + uint32_t *y_offset_sa) +{ + assert(level < surf->levels); + assert(surf->logical_level0_px.depth == 1); + assert(logical_array_layer < surf->logical_level0_px.array_len); + + const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); + + const struct isl_extent3d image_align_sa = + isl_surf_get_image_alignment_sa(surf); + + struct isl_tile_info tile_info; + isl_tiling_get_info(surf->tiling, fmtl->bpb, &tile_info); + const struct isl_extent2d tile_extent_sa = { + .w = tile_info.logical_extent_el.w * fmtl->bw, + .h = tile_info.logical_extent_el.h * fmtl->bh, + }; + /* Tile size is a multiple of image alignment */ + assert(tile_extent_sa.w % image_align_sa.w == 0); + assert(tile_extent_sa.h % image_align_sa.h == 0); + + const uint32_t W0 = surf->phys_level0_sa.w; + const uint32_t H0 = surf->phys_level0_sa.h; + + /* Each image has the same height as LOD0 because the hardware thinks + * everything is LOD0 + */ + const uint32_t H = isl_align(H0, image_align_sa.h); + + /* Quick sanity check for consistency */ + if (surf->phys_level0_sa.array_len > 1) + assert(surf->array_pitch_el_rows == isl_assert_div(H, fmtl->bh)); + + uint32_t x = 0, y = 0; + for (uint32_t l = 0; l < level; ++l) { + const uint32_t W = isl_minify(W0, l); + + const uint32_t w = isl_align(W, tile_extent_sa.w); + const uint32_t h = isl_align(H * surf->phys_level0_sa.a, + tile_extent_sa.h); + + if (l == 0) { + y += h; + } else { + x += w; + } + } + + y += H * logical_array_layer; + + *x_offset_sa = x; + *y_offset_sa = y; +} + /** * A variant of isl_surf_get_image_offset_sa() specific to * ISL_DIM_LAYOUT_GEN9_1D. @@ -1933,6 +2513,11 @@ isl_surf_get_image_offset_sa(const struct isl_surf *surf, logical_z_offset_px, x_offset_sa, y_offset_sa); break; + case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ: + get_image_offset_sa_gen6_stencil_hiz(surf, level, logical_array_layer + + logical_z_offset_px, + x_offset_sa, y_offset_sa); + break; default: unreachable("not reached"); @@ -1965,10 +2550,140 @@ isl_surf_get_image_offset_el(const struct isl_surf *surf, *y_offset_el = y_offset_sa / fmtl->bh; } +void +isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf, + uint32_t level, + uint32_t logical_array_layer, + uint32_t logical_z_offset_px, + uint32_t *offset_B, + uint32_t *x_offset_sa, + uint32_t *y_offset_sa) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); + + uint32_t total_x_offset_el, total_y_offset_el; + isl_surf_get_image_offset_el(surf, level, logical_array_layer, + logical_z_offset_px, + &total_x_offset_el, + &total_y_offset_el); + + uint32_t x_offset_el, y_offset_el; + isl_tiling_get_intratile_offset_el(surf->tiling, fmtl->bpb, + surf->row_pitch_B, + total_x_offset_el, + total_y_offset_el, + offset_B, + &x_offset_el, + &y_offset_el); + + if (x_offset_sa) { + *x_offset_sa = x_offset_el * fmtl->bw; + } else { + assert(x_offset_el == 0); + } + + if (y_offset_sa) { + *y_offset_sa = y_offset_el * fmtl->bh; + } else { + assert(y_offset_el == 0); + } +} + +void +isl_surf_get_image_range_B_tile(const struct isl_surf *surf, + uint32_t level, + uint32_t logical_array_layer, + uint32_t logical_z_offset_px, + uint32_t *start_tile_B, + uint32_t *end_tile_B) +{ + uint32_t start_x_offset_el, start_y_offset_el; + isl_surf_get_image_offset_el(surf, level, logical_array_layer, + logical_z_offset_px, + &start_x_offset_el, + &start_y_offset_el); + + /* Compute the size of the subimage in surface elements */ + const uint32_t subimage_w_sa = isl_minify(surf->phys_level0_sa.w, level); + const uint32_t subimage_h_sa = isl_minify(surf->phys_level0_sa.h, level); + const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); + const uint32_t subimage_w_el = isl_align_div_npot(subimage_w_sa, fmtl->bw); + const uint32_t subimage_h_el = isl_align_div_npot(subimage_h_sa, fmtl->bh); + + /* Find the last pixel */ + uint32_t end_x_offset_el = start_x_offset_el + subimage_w_el - 1; + uint32_t end_y_offset_el = start_y_offset_el + subimage_h_el - 1; + + UNUSED uint32_t x_offset_el, y_offset_el; + isl_tiling_get_intratile_offset_el(surf->tiling, fmtl->bpb, + surf->row_pitch_B, + start_x_offset_el, + start_y_offset_el, + start_tile_B, + &x_offset_el, + &y_offset_el); + + isl_tiling_get_intratile_offset_el(surf->tiling, fmtl->bpb, + surf->row_pitch_B, + end_x_offset_el, + end_y_offset_el, + end_tile_B, + &x_offset_el, + &y_offset_el); + + /* We want the range we return to be exclusive but the tile containing the + * last pixel (what we just calculated) is inclusive. Add one. + */ + (*end_tile_B)++; + + assert(*end_tile_B <= surf->size_B); +} + +void +isl_surf_get_image_surf(const struct isl_device *dev, + const struct isl_surf *surf, + uint32_t level, + uint32_t logical_array_layer, + uint32_t logical_z_offset_px, + struct isl_surf *image_surf, + uint32_t *offset_B, + uint32_t *x_offset_sa, + uint32_t *y_offset_sa) +{ + isl_surf_get_image_offset_B_tile_sa(surf, + level, + logical_array_layer, + logical_z_offset_px, + offset_B, + x_offset_sa, + y_offset_sa); + + /* Even for cube maps there will be only single face, therefore drop the + * corresponding flag if present. + */ + const isl_surf_usage_flags_t usage = + surf->usage & (~ISL_SURF_USAGE_CUBE_BIT); + + bool ok UNUSED; + ok = isl_surf_init(dev, image_surf, + .dim = ISL_SURF_DIM_2D, + .format = surf->format, + .width = isl_minify(surf->logical_level0_px.w, level), + .height = isl_minify(surf->logical_level0_px.h, level), + .depth = 1, + .levels = 1, + .array_len = 1, + .samples = surf->samples, + .row_pitch_B = surf->row_pitch_B, + .usage = usage, + .tiling_flags = (1 << surf->tiling)); + assert(ok); +} + void isl_tiling_get_intratile_offset_el(enum isl_tiling tiling, - uint8_t bs, - uint32_t row_pitch, + uint32_t bpb, + uint32_t row_pitch_B, uint32_t total_x_offset_el, uint32_t total_y_offset_el, uint32_t *base_address_offset, @@ -1976,19 +2691,18 @@ isl_tiling_get_intratile_offset_el(enum isl_tiling tiling, uint32_t *y_offset_el) { if (tiling == ISL_TILING_LINEAR) { - *base_address_offset = total_y_offset_el * row_pitch + - total_x_offset_el * bs; + assert(bpb % 8 == 0); + *base_address_offset = total_y_offset_el * row_pitch_B + + total_x_offset_el * (bpb / 8); *x_offset_el = 0; *y_offset_el = 0; return; } - const uint32_t bpb = bs * 8; - struct isl_tile_info tile_info; isl_tiling_get_info(tiling, bpb, &tile_info); - assert(row_pitch % tile_info.phys_extent_B.width == 0); + assert(row_pitch_B % tile_info.phys_extent_B.width == 0); /* For non-power-of-two formats, we need the address to be both tile and * element-aligned. The easiest way to achieve this is to work with a tile @@ -2011,7 +2725,7 @@ isl_tiling_get_intratile_offset_el(enum isl_tiling tiling, uint32_t y_offset_tl = total_y_offset_el / tile_info.logical_extent_el.h; *base_address_offset = - y_offset_tl * tile_info.phys_extent_B.h * row_pitch + + y_offset_tl * tile_info.phys_extent_B.h * row_pitch_B + x_offset_tl * tile_info.phys_extent_B.h * tile_info.phys_extent_B.w; } @@ -2058,3 +2772,216 @@ isl_surf_get_depth_format(const struct isl_device *dev, return 5; /* D16_UNORM */ } } + +bool +isl_swizzle_supports_rendering(const struct gen_device_info *devinfo, + struct isl_swizzle swizzle) +{ + if (devinfo->is_haswell) { + /* From the Haswell PRM, + * RENDER_SURFACE_STATE::Shader Channel Select Red + * + * "The Shader channel selects also define which shader channels are + * written to which surface channel. If the Shader channel select is + * SCS_ZERO or SCS_ONE then it is not written to the surface. If the + * shader channel select is SCS_RED it is written to the surface red + * channel and so on. If more than one shader channel select is set + * to the same surface channel only the first shader channel in RGBA + * order will be written." + */ + return true; + } else if (devinfo->gen <= 7) { + /* Ivy Bridge and early doesn't have any swizzling */ + return isl_swizzle_is_identity(swizzle); + } else { + /* From the Sky Lake PRM Vol. 2d, + * RENDER_SURFACE_STATE::Shader Channel Select Red + * + * "For Render Target, Red, Green and Blue Shader Channel Selects + * MUST be such that only valid components can be swapped i.e. only + * change the order of components in the pixel. Any other values for + * these Shader Channel Select fields are not valid for Render + * Targets. This also means that there MUST not be multiple shader + * channels mapped to the same RT channel." + * + * From the Sky Lake PRM Vol. 2d, + * RENDER_SURFACE_STATE::Shader Channel Select Alpha + * + * "For Render Target, this field MUST be programmed to + * value = SCS_ALPHA." + */ + return (swizzle.r == ISL_CHANNEL_SELECT_RED || + swizzle.r == ISL_CHANNEL_SELECT_GREEN || + swizzle.r == ISL_CHANNEL_SELECT_BLUE) && + (swizzle.g == ISL_CHANNEL_SELECT_RED || + swizzle.g == ISL_CHANNEL_SELECT_GREEN || + swizzle.g == ISL_CHANNEL_SELECT_BLUE) && + (swizzle.b == ISL_CHANNEL_SELECT_RED || + swizzle.b == ISL_CHANNEL_SELECT_GREEN || + swizzle.b == ISL_CHANNEL_SELECT_BLUE) && + swizzle.r != swizzle.g && + swizzle.r != swizzle.b && + swizzle.g != swizzle.b && + swizzle.a == ISL_CHANNEL_SELECT_ALPHA; + } +} + +static enum isl_channel_select +swizzle_select(enum isl_channel_select chan, struct isl_swizzle swizzle) +{ + switch (chan) { + case ISL_CHANNEL_SELECT_ZERO: + case ISL_CHANNEL_SELECT_ONE: + return chan; + case ISL_CHANNEL_SELECT_RED: + return swizzle.r; + case ISL_CHANNEL_SELECT_GREEN: + return swizzle.g; + case ISL_CHANNEL_SELECT_BLUE: + return swizzle.b; + case ISL_CHANNEL_SELECT_ALPHA: + return swizzle.a; + default: + unreachable("Invalid swizzle component"); + } +} + +/** + * Returns the single swizzle that is equivalent to applying the two given + * swizzles in sequence. + */ +struct isl_swizzle +isl_swizzle_compose(struct isl_swizzle first, struct isl_swizzle second) +{ + return (struct isl_swizzle) { + .r = swizzle_select(first.r, second), + .g = swizzle_select(first.g, second), + .b = swizzle_select(first.b, second), + .a = swizzle_select(first.a, second), + }; +} + +/** + * Returns a swizzle that is the pseudo-inverse of this swizzle. + */ +struct isl_swizzle +isl_swizzle_invert(struct isl_swizzle swizzle) +{ + /* Default to zero for channels which do not show up in the swizzle */ + enum isl_channel_select chans[4] = { + ISL_CHANNEL_SELECT_ZERO, + ISL_CHANNEL_SELECT_ZERO, + ISL_CHANNEL_SELECT_ZERO, + ISL_CHANNEL_SELECT_ZERO, + }; + + /* We go in ABGR order so that, if there are any duplicates, the first one + * is taken if you look at it in RGBA order. This is what Haswell hardware + * does for render target swizzles. + */ + if ((unsigned)(swizzle.a - ISL_CHANNEL_SELECT_RED) < 4) + chans[swizzle.a - ISL_CHANNEL_SELECT_RED] = ISL_CHANNEL_SELECT_ALPHA; + if ((unsigned)(swizzle.b - ISL_CHANNEL_SELECT_RED) < 4) + chans[swizzle.b - ISL_CHANNEL_SELECT_RED] = ISL_CHANNEL_SELECT_BLUE; + if ((unsigned)(swizzle.g - ISL_CHANNEL_SELECT_RED) < 4) + chans[swizzle.g - ISL_CHANNEL_SELECT_RED] = ISL_CHANNEL_SELECT_GREEN; + if ((unsigned)(swizzle.r - ISL_CHANNEL_SELECT_RED) < 4) + chans[swizzle.r - ISL_CHANNEL_SELECT_RED] = ISL_CHANNEL_SELECT_RED; + + return (struct isl_swizzle) { chans[0], chans[1], chans[2], chans[3] }; +} + +/** Applies an inverse swizzle to a color value */ +union isl_color_value +isl_color_value_swizzle_inv(union isl_color_value src, + struct isl_swizzle swizzle) +{ + union isl_color_value dst = { .u32 = { 0, } }; + + /* We assign colors in ABGR order so that the first one will be taken in + * RGBA precedence order. According to the PRM docs for shader channel + * select, this matches Haswell hardware behavior. + */ + if ((unsigned)(swizzle.a - ISL_CHANNEL_SELECT_RED) < 4) + dst.u32[swizzle.a - ISL_CHANNEL_SELECT_RED] = src.u32[3]; + if ((unsigned)(swizzle.b - ISL_CHANNEL_SELECT_RED) < 4) + dst.u32[swizzle.b - ISL_CHANNEL_SELECT_RED] = src.u32[2]; + if ((unsigned)(swizzle.g - ISL_CHANNEL_SELECT_RED) < 4) + dst.u32[swizzle.g - ISL_CHANNEL_SELECT_RED] = src.u32[1]; + if ((unsigned)(swizzle.r - ISL_CHANNEL_SELECT_RED) < 4) + dst.u32[swizzle.r - ISL_CHANNEL_SELECT_RED] = src.u32[0]; + + return dst; +} + +uint8_t +isl_format_get_aux_map_encoding(enum isl_format format) +{ + switch(format) { + case ISL_FORMAT_R32G32B32A32_FLOAT: return 0x11; + case ISL_FORMAT_R32G32B32X32_FLOAT: return 0x11; + case ISL_FORMAT_R32G32B32A32_SINT: return 0x12; + case ISL_FORMAT_R32G32B32A32_UINT: return 0x13; + case ISL_FORMAT_R16G16B16A16_UNORM: return 0x14; + case ISL_FORMAT_R16G16B16A16_SNORM: return 0x15; + case ISL_FORMAT_R16G16B16A16_SINT: return 0x16; + case ISL_FORMAT_R16G16B16A16_UINT: return 0x17; + case ISL_FORMAT_R16G16B16A16_FLOAT: return 0x10; + case ISL_FORMAT_R16G16B16X16_FLOAT: return 0x10; + case ISL_FORMAT_R32G32_FLOAT: return 0x11; + case ISL_FORMAT_R32G32_SINT: return 0x12; + case ISL_FORMAT_R32G32_UINT: return 0x13; + case ISL_FORMAT_B8G8R8A8_UNORM: return 0xA; + case ISL_FORMAT_B8G8R8X8_UNORM: return 0xA; + case ISL_FORMAT_B8G8R8A8_UNORM_SRGB: return 0xA; + case ISL_FORMAT_B8G8R8X8_UNORM_SRGB: return 0xA; + case ISL_FORMAT_R10G10B10A2_UNORM: return 0x18; + case ISL_FORMAT_R10G10B10A2_UNORM_SRGB: return 0x18; + case ISL_FORMAT_R10G10B10_FLOAT_A2_UNORM: return 0x19; + case ISL_FORMAT_R10G10B10A2_UINT: return 0x1A; + case ISL_FORMAT_R8G8B8A8_UNORM: return 0xA; + case ISL_FORMAT_R8G8B8A8_UNORM_SRGB: return 0xA; + case ISL_FORMAT_R8G8B8A8_SNORM: return 0x1B; + case ISL_FORMAT_R8G8B8A8_SINT: return 0x1C; + case ISL_FORMAT_R8G8B8A8_UINT: return 0x1D; + case ISL_FORMAT_R16G16_UNORM: return 0x14; + case ISL_FORMAT_R16G16_SNORM: return 0x15; + case ISL_FORMAT_R16G16_SINT: return 0x16; + case ISL_FORMAT_R16G16_UINT: return 0x17; + case ISL_FORMAT_R16G16_FLOAT: return 0x10; + case ISL_FORMAT_B10G10R10A2_UNORM: return 0x18; + case ISL_FORMAT_B10G10R10A2_UNORM_SRGB: return 0x18; + case ISL_FORMAT_R11G11B10_FLOAT: return 0x1E; + case ISL_FORMAT_R32_SINT: return 0x12; + case ISL_FORMAT_R32_UINT: return 0x13; + case ISL_FORMAT_R32_FLOAT: return 0x11; + case ISL_FORMAT_R24_UNORM_X8_TYPELESS: return 0x11; + case ISL_FORMAT_B5G6R5_UNORM: return 0xA; + case ISL_FORMAT_B5G6R5_UNORM_SRGB: return 0xA; + case ISL_FORMAT_B5G5R5A1_UNORM: return 0xA; + case ISL_FORMAT_B5G5R5A1_UNORM_SRGB: return 0xA; + case ISL_FORMAT_B4G4R4A4_UNORM: return 0xA; + case ISL_FORMAT_B4G4R4A4_UNORM_SRGB: return 0xA; + case ISL_FORMAT_R8G8_UNORM: return 0xA; + case ISL_FORMAT_R8G8_SNORM: return 0x1B; + case ISL_FORMAT_R8G8_SINT: return 0x1C; + case ISL_FORMAT_R8G8_UINT: return 0x1D; + case ISL_FORMAT_R16_UNORM: return 0x14; + case ISL_FORMAT_R16_SNORM: return 0x15; + case ISL_FORMAT_R16_SINT: return 0x16; + case ISL_FORMAT_R16_UINT: return 0x17; + case ISL_FORMAT_R16_FLOAT: return 0x10; + case ISL_FORMAT_B5G5R5X1_UNORM: return 0xA; + case ISL_FORMAT_B5G5R5X1_UNORM_SRGB: return 0xA; + case ISL_FORMAT_A1B5G5R5_UNORM: return 0xA; + case ISL_FORMAT_A4B4G4R4_UNORM: return 0xA; + case ISL_FORMAT_R8_UNORM: return 0xA; + case ISL_FORMAT_R8_SNORM: return 0x1B; + case ISL_FORMAT_R8_SINT: return 0x1C; + case ISL_FORMAT_R8_UINT: return 0x1D; + case ISL_FORMAT_A8_UNORM: return 0xA; + default: + unreachable("Unsupported aux-map format!"); + return 0; + } +}