X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fintel%2Fisl%2Fisl.h;h=9fbc88ec83ed38159cf3529babf8c5c4672a2db0;hb=de17922b8a3c382cf89833cf8975cadc00142313;hp=b9f9fb60d07ef9af2fb4f0ffff97dfbe24fb25a2;hpb=268ba028dcbdaea25a972a460c1636f485d5c5bc;p=mesa.git diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index b9f9fb60d07..9fbc88ec83e 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -389,6 +389,9 @@ enum isl_format { ISL_FORMAT_GEN9_CCS_64BPP, ISL_FORMAT_GEN9_CCS_128BPP, + /* An upper bound on the supported format enumerations */ + ISL_NUM_FORMATS, + /* Hardware doesn't understand this out-of-band value */ ISL_FORMAT_UNSUPPORTED = UINT16_MAX, }; @@ -661,31 +664,8 @@ enum isl_aux_usage { * * Drawing with or without aux enabled may implicitly cause the surface to * transition between these states. There are also four types of auxiliary - * compression operations which cause an explicit transition: - * - * 1) Fast Clear: This operation writes the magic "clear" value to the - * auxiliary surface. This operation will safely transition any slice - * of a surface from any state to the clear state so long as the entire - * slice is fast cleared at once. A fast clear that only covers part of - * a slice of a surface is called a partial fast clear. - * - * 2) Full Resolve: This operation combines the auxiliary surface data - * with the primary surface data and writes the result to the primary. - * For HiZ, the docs call this a depth resolve. For CCS, the hardware - * full resolve operation does both a full resolve and an ambiguate so - * it actually takes you all the way to the pass-through state. - * - * 3) Partial Resolve: This operation considers blocks which are in the - * "clear" state and writes the clear value directly into the primary or - * auxiliary surface. Once this operation completes, the surface is - * still compressed but no longer references the clear color. This - * operation is only available for CCS. - * - * 4) Ambiguate: This operation throws away the current auxiliary data and - * replaces it with the magic pass-through value. If an ambiguate - * operation is performed when the primary surface does not contain 100% - * of the data, data will be lost. This operation is only implemented - * in hardware for depth where it is called a HiZ resolve. + * compression operations which cause an explicit transition which are + * described by the isl_aux_op enum below. * * Not all operations are valid or useful in all states. The diagram below * contains a complete description of the states and all valid and useful @@ -787,6 +767,53 @@ enum isl_aux_state { ISL_AUX_STATE_AUX_INVALID, }; +/** + * Enum which describes explicit aux transition operations. + */ +enum isl_aux_op { + ISL_AUX_OP_NONE, + + /** Fast Clear + * + * This operation writes the magic "clear" value to the auxiliary surface. + * This operation will safely transition any slice of a surface from any + * state to the clear state so long as the entire slice is fast cleared at + * once. A fast clear that only covers part of a slice of a surface is + * called a partial fast clear. + */ + ISL_AUX_OP_FAST_CLEAR, + + /** Full Resolve + * + * This operation combines the auxiliary surface data with the primary + * surface data and writes the result to the primary. For HiZ, the docs + * call this a depth resolve. For CCS, the hardware full resolve operation + * does both a full resolve and an ambiguate so it actually takes you all + * the way to the pass-through state. + */ + ISL_AUX_OP_FULL_RESOLVE, + + /** Partial Resolve + * + * This operation considers blocks which are in the "clear" state and + * writes the clear value directly into the primary or auxiliary surface. + * Once this operation completes, the surface is still compressed but no + * longer references the clear color. This operation is only available + * for CCS_E. + */ + ISL_AUX_OP_PARTIAL_RESOLVE, + + /** Ambiguate + * + * This operation throws away the current auxiliary data and replaces it + * with the magic pass-through value. If an ambiguate operation is + * performed when the primary surface does not contain 100% of the data, + * data will be lost. This operation is only implemented in hardware for + * depth where it is called a HiZ resolve. + */ + ISL_AUX_OP_AMBIGUATE, +}; + /* TODO(chadv): Explain */ enum isl_array_pitch_span { ISL_ARRAY_PITCH_SPAN_FULL, @@ -834,7 +861,7 @@ typedef uint8_t isl_channel_mask_t; /** * @brief A channel select (also known as texture swizzle) value */ -enum isl_channel_select { +enum PACKED isl_channel_select { ISL_CHANNEL_SELECT_ZERO = 0, ISL_CHANNEL_SELECT_ONE = 1, ISL_CHANNEL_SELECT_RED = 4, @@ -922,6 +949,12 @@ enum isl_msaa_layout { ISL_MSAA_LAYOUT_ARRAY, }; +typedef enum { + ISL_MEMCPY = 0, + ISL_MEMCPY_BGRA8, + ISL_MEMCPY_STREAMING_LOAD, + ISL_MEMCPY_INVALID, +} isl_memcpy_type; struct isl_device { const struct gen_device_info *info; @@ -939,6 +972,12 @@ struct isl_device { uint8_t aux_addr_offset; /* Rounded up to the nearest dword to simplify GPU memcpy operations. */ + + /* size of the state buffer used to store the clear color + extra + * additional space used by the hardware */ + uint8_t clear_color_state_size; + uint8_t clear_color_state_offset; + /* size of the clear color itself - used to copy it to/from a BO */ uint8_t clear_value_size; uint8_t clear_value_offset; } ss; @@ -975,6 +1014,7 @@ struct isl_extent4d { struct isl_channel_layout { enum isl_base_type type; + uint8_t start_bit; /**< Bit at which this channel starts */ uint8_t bits; /**< Size in bits */ }; @@ -994,15 +1034,18 @@ struct isl_format_layout { uint8_t bh; /**< Block height, in pixels */ uint8_t bd; /**< Block depth, in pixels */ - struct { - struct isl_channel_layout r; /**< Red channel */ - struct isl_channel_layout g; /**< Green channel */ - struct isl_channel_layout b; /**< Blue channel */ - struct isl_channel_layout a; /**< Alpha channel */ - struct isl_channel_layout l; /**< Luminance channel */ - struct isl_channel_layout i; /**< Intensity channel */ - struct isl_channel_layout p; /**< Palette channel */ - } channels; + union { + struct { + struct isl_channel_layout r; /**< Red channel */ + struct isl_channel_layout g; /**< Green channel */ + struct isl_channel_layout b; /**< Blue channel */ + struct isl_channel_layout a; /**< Alpha channel */ + struct isl_channel_layout l; /**< Luminance channel */ + struct isl_channel_layout i; /**< Intensity channel */ + struct isl_channel_layout p; /**< Palette channel */ + } channels; + struct isl_channel_layout channels_array[7]; + }; enum isl_colorspace colorspace; enum isl_txc txc; @@ -1048,7 +1091,7 @@ struct isl_tile_info { * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but * its physical size is 128B x 32rows, the same as a Y-tile. * - * @see isl_surf::row_pitch + * @see isl_surf::row_pitch_B */ struct isl_extent2d phys_extent_B; }; @@ -1098,13 +1141,13 @@ struct isl_surf_init_info { uint32_t samples; /** Lower bound for isl_surf::alignment, in bytes. */ - uint32_t min_alignment; + uint32_t min_alignment_B; /** * Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init() * will fail if this is misaligned or out of bounds. */ - uint32_t row_pitch; + uint32_t row_pitch_B; isl_surf_usage_flags_t usage; @@ -1133,7 +1176,7 @@ struct isl_surf { /** * Physical extent of the surface's base level, in units of physical - * surface samples and aligned to the format's compression block. + * surface samples. * * Consider isl_dim_layout as an operator that transforms a logical surface * layout to a physical surface layout. Then @@ -1147,17 +1190,17 @@ struct isl_surf { uint32_t samples; /** Total size of the surface, in bytes. */ - uint64_t size; + uint64_t size_B; /** Required alignment for the surface's base address. */ - uint32_t alignment; + uint32_t alignment_B; /** * The interpretation of this field depends on the value of * isl_tile_info::physical_extent_B. In particular, the width of the - * surface in tiles is row_pitch / isl_tile_info::physical_extent_B.width + * surface in tiles is row_pitch_B / isl_tile_info::physical_extent_B.width * and the distance in bytes between vertically adjacent tiles in the image - * is given by row_pitch * isl_tile_info::physical_extent_B.height. + * is given by row_pitch_B * isl_tile_info::physical_extent_B.height. * * For linear images where isl_tile_info::physical_extent_B.height == 1, * this cleanly reduces to being the distance, in bytes, between vertically @@ -1165,7 +1208,7 @@ struct isl_surf { * * @see isl_tile_info::phys_extent_B; */ - uint32_t row_pitch; + uint32_t row_pitch_B; /** * Pitch between physical array slices, in rows of surface elements. @@ -1274,6 +1317,15 @@ struct isl_surf_fill_state_info { */ union isl_color_value clear_color; + /** + * Send only the clear value address + * + * If set, we only pass the clear address to the GPU and it will fetch it + * from wherever it is. + */ + bool use_clear_address; + uint64_t clear_address; + /** * Surface write disables for gen4-5 */ @@ -1292,7 +1344,7 @@ struct isl_buffer_fill_state_info { /** * The size of the buffer */ - uint64_t size; + uint64_t size_B; /** * The Memory Object Control state for the filled surface state. @@ -1309,7 +1361,12 @@ struct isl_buffer_fill_state_info { */ enum isl_format format; - uint32_t stride; + /** + * The swizzle to use in the surface state + */ + struct isl_swizzle swizzle; + + uint32_t stride_B; }; struct isl_depth_stencil_hiz_emit_info { @@ -1380,13 +1437,17 @@ isl_device_get_sample_counts(struct isl_device *dev); static inline const struct isl_format_layout * ATTRIBUTE_CONST isl_format_get_layout(enum isl_format fmt) { + assert(fmt != ISL_FORMAT_UNSUPPORTED); + assert(fmt < ISL_NUM_FORMATS); return &isl_format_layouts[fmt]; } +bool isl_format_is_valid(enum isl_format); + static inline const char * ATTRIBUTE_CONST isl_format_get_name(enum isl_format fmt) { - return isl_format_layouts[fmt].name; + return isl_format_get_layout(fmt)->name; } bool isl_format_supports_rendering(const struct gen_device_info *devinfo, @@ -1442,6 +1503,9 @@ isl_format_has_int_channel(enum isl_format fmt) isl_format_has_sint_channel(fmt); } +bool isl_format_has_color_component(enum isl_format fmt, + int component) ATTRIBUTE_CONST; + unsigned isl_format_get_num_channels(enum isl_format fmt); uint32_t isl_format_get_depth_format(enum isl_format fmt, bool has_stencil); @@ -1498,17 +1562,50 @@ isl_format_block_is_1x1x1(enum isl_format fmt) return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1; } +static inline bool +isl_format_is_srgb(enum isl_format fmt) +{ + return isl_format_get_layout(fmt)->colorspace == ISL_COLORSPACE_SRGB; +} + +enum isl_format isl_format_srgb_to_linear(enum isl_format fmt); + static inline bool isl_format_is_rgb(enum isl_format fmt) { - return isl_format_layouts[fmt].channels.r.bits > 0 && - isl_format_layouts[fmt].channels.g.bits > 0 && - isl_format_layouts[fmt].channels.b.bits > 0 && - isl_format_layouts[fmt].channels.a.bits == 0; + if (isl_format_is_yuv(fmt)) + return false; + + const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); + + return fmtl->channels.r.bits > 0 && + fmtl->channels.g.bits > 0 && + fmtl->channels.b.bits > 0 && + fmtl->channels.a.bits == 0; +} + +static inline bool +isl_format_is_rgbx(enum isl_format fmt) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); + + return fmtl->channels.r.bits > 0 && + fmtl->channels.g.bits > 0 && + fmtl->channels.b.bits > 0 && + fmtl->channels.a.bits > 0 && + fmtl->channels.a.type == ISL_VOID; } enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST; enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST; +enum isl_format isl_format_rgbx_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST; + +void isl_color_value_pack(const union isl_color_value *value, + enum isl_format format, + uint32_t *data_out); +void isl_color_value_unpack(union isl_color_value *value, + enum isl_format format, + const uint32_t *data_in); bool isl_is_storage_image_format(enum isl_format fmt); @@ -1544,6 +1641,48 @@ isl_tiling_from_i915_tiling(uint32_t tiling); const struct isl_drm_modifier_info * ATTRIBUTE_CONST isl_drm_modifier_get_info(uint64_t modifier); +static inline bool +isl_drm_modifier_has_aux(uint64_t modifier) +{ + return isl_drm_modifier_get_info(modifier)->aux_usage != ISL_AUX_USAGE_NONE; +} + +/** Returns the default isl_aux_state for the given modifier. + * + * If we have a modifier which supports compression, then the auxiliary data + * could be in state other than ISL_AUX_STATE_AUX_INVALID. In particular, it + * can be in any of the following: + * + * - ISL_AUX_STATE_CLEAR + * - ISL_AUX_STATE_PARTIAL_CLEAR + * - ISL_AUX_STATE_COMPRESSED_CLEAR + * - ISL_AUX_STATE_COMPRESSED_NO_CLEAR + * - ISL_AUX_STATE_RESOLVED + * - ISL_AUX_STATE_PASS_THROUGH + * + * If the modifier does not support fast-clears, then we are guaranteed + * that the surface is at least partially resolved and the first three not + * possible. We return ISL_AUX_STATE_COMPRESSED_CLEAR if the modifier + * supports fast clears and ISL_AUX_STATE_COMPRESSED_NO_CLEAR if it does not + * because they are the least common denominator of the set of possible aux + * states and will yield a valid interpretation of the aux data. + * + * For modifiers with no aux support, ISL_AUX_STATE_AUX_INVALID is returned. + */ +static inline enum isl_aux_state +isl_drm_modifier_get_default_aux_state(uint64_t modifier) +{ + const struct isl_drm_modifier_info *mod_info = + isl_drm_modifier_get_info(modifier); + + if (!mod_info || mod_info->aux_usage == ISL_AUX_USAGE_NONE) + return ISL_AUX_STATE_AUX_INVALID; + + assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E); + return mod_info->supports_clear_color ? ISL_AUX_STATE_COMPRESSED_CLEAR : + ISL_AUX_STATE_COMPRESSED_NO_CLEAR; +} + struct isl_extent2d ATTRIBUTE_CONST isl_get_interleaved_msaa_px_size_sa(uint32_t samples); @@ -1629,6 +1768,30 @@ isl_extent4d(uint32_t width, uint32_t height, uint32_t depth, return e; } +bool isl_color_value_is_zero(union isl_color_value value, + enum isl_format format); + +bool isl_color_value_is_zero_one(union isl_color_value value, + enum isl_format format); + +static inline bool +isl_swizzle_is_identity(struct isl_swizzle swizzle) +{ + return swizzle.r == ISL_CHANNEL_SELECT_RED && + swizzle.g == ISL_CHANNEL_SELECT_GREEN && + swizzle.b == ISL_CHANNEL_SELECT_BLUE && + swizzle.a == ISL_CHANNEL_SELECT_ALPHA; +} + +bool +isl_swizzle_supports_rendering(const struct gen_device_info *devinfo, + struct isl_swizzle swizzle); + +struct isl_swizzle +isl_swizzle_compose(struct isl_swizzle first, struct isl_swizzle second); +struct isl_swizzle +isl_swizzle_invert(struct isl_swizzle swizzle); + #define isl_surf_init(dev, surf, ...) \ isl_surf_init_s((dev), (surf), \ &(struct isl_surf_init_info) { __VA_ARGS__ }); @@ -1656,7 +1819,7 @@ bool isl_surf_get_ccs_surf(const struct isl_device *dev, const struct isl_surf *surf, struct isl_surf *ccs_surf, - uint32_t row_pitch /**< Ignored if 0 */); + uint32_t row_pitch_B /**< Ignored if 0 */); #define isl_surf_fill_state(dev, state, ...) \ isl_surf_fill_state_s((dev), (state), \ @@ -1674,6 +1837,10 @@ void isl_buffer_fill_state_s(const struct isl_device *dev, void *state, const struct isl_buffer_fill_state_info *restrict info); +void +isl_null_fill_state(const struct isl_device *dev, void *state, + struct isl_extent3d size); + #define isl_emit_depth_stencil_hiz(dev, batch, ...) \ isl_emit_depth_stencil_hiz_s((dev), (batch), \ &(struct isl_depth_stencil_hiz_emit_info) { __VA_ARGS__ }) @@ -1718,13 +1885,41 @@ isl_surf_get_image_alignment_sa(const struct isl_surf *surf) fmtl->bd * surf->image_alignment_el.d); } +/** + * Logical extent of level 0 in units of surface elements. + */ +static inline struct isl_extent4d +isl_surf_get_logical_level0_el(const struct isl_surf *surf) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); + + return isl_extent4d(DIV_ROUND_UP(surf->logical_level0_px.w, fmtl->bw), + DIV_ROUND_UP(surf->logical_level0_px.h, fmtl->bh), + DIV_ROUND_UP(surf->logical_level0_px.d, fmtl->bd), + surf->logical_level0_px.a); +} + +/** + * Physical extent of level 0 in units of surface elements. + */ +static inline struct isl_extent4d +isl_surf_get_phys_level0_el(const struct isl_surf *surf) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); + + return isl_extent4d(DIV_ROUND_UP(surf->phys_level0_sa.w, fmtl->bw), + DIV_ROUND_UP(surf->phys_level0_sa.h, fmtl->bh), + DIV_ROUND_UP(surf->phys_level0_sa.d, fmtl->bd), + surf->phys_level0_sa.a); +} + /** * Pitch between vertically adjacent surface elements, in bytes. */ static inline uint32_t -isl_surf_get_row_pitch(const struct isl_surf *surf) +isl_surf_get_row_pitch_B(const struct isl_surf *surf) { - return surf->row_pitch; + return surf->row_pitch_B; } /** @@ -1735,8 +1930,8 @@ isl_surf_get_row_pitch_el(const struct isl_surf *surf) { const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); - assert(surf->row_pitch % (fmtl->bpb / 8) == 0); - return surf->row_pitch / (fmtl->bpb / 8); + assert(surf->row_pitch_B % (fmtl->bpb / 8) == 0); + return surf->row_pitch_B / (fmtl->bpb / 8); } /** @@ -1774,7 +1969,7 @@ isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf) static inline uint32_t isl_surf_get_array_pitch(const struct isl_surf *surf) { - return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch; + return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch_B; } /** @@ -1830,6 +2025,29 @@ isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf, uint32_t *x_offset_sa, uint32_t *y_offset_sa); +/** + * Create an isl_surf that represents a particular subimage in the surface. + * + * The newly created surface will have a single miplevel and array slice. The + * surface lives at the returned byte and intratile offsets, in samples. + * + * It is safe to call this function with surf == image_surf. + * + * @invariant level < surface levels + * @invariant logical_array_layer < logical array length of surface + * @invariant logical_z_offset_px < logical depth of surface at level + */ +void +isl_surf_get_image_surf(const struct isl_device *dev, + const struct isl_surf *surf, + uint32_t level, + uint32_t logical_array_layer, + uint32_t logical_z_offset_px, + struct isl_surf *image_surf, + uint32_t *offset_B, + uint32_t *x_offset_sa, + uint32_t *y_offset_sa); + /** * @brief Calculate the intratile offsets to a surface. * @@ -1843,7 +2061,7 @@ isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf, void isl_tiling_get_intratile_offset_el(enum isl_tiling tiling, uint32_t bpb, - uint32_t row_pitch, + uint32_t row_pitch_B, uint32_t total_x_offset_el, uint32_t total_y_offset_el, uint32_t *base_address_offset, @@ -1853,7 +2071,7 @@ isl_tiling_get_intratile_offset_el(enum isl_tiling tiling, static inline void isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling, enum isl_format format, - uint32_t row_pitch, + uint32_t row_pitch_B, uint32_t total_x_offset_sa, uint32_t total_y_offset_sa, uint32_t *base_address_offset, @@ -1871,7 +2089,7 @@ isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling, const uint32_t total_x_offset = total_x_offset_sa / fmtl->bw; const uint32_t total_y_offset = total_y_offset_sa / fmtl->bh; - isl_tiling_get_intratile_offset_el(tiling, fmtl->bpb, row_pitch, + isl_tiling_get_intratile_offset_el(tiling, fmtl->bpb, row_pitch_B, total_x_offset, total_y_offset, base_address_offset, x_offset_sa, y_offset_sa); @@ -1889,6 +2107,32 @@ uint32_t isl_surf_get_depth_format(const struct isl_device *dev, const struct isl_surf *surf); +/** + * @brief performs a copy from linear to tiled surface + * + */ +void +isl_memcpy_linear_to_tiled(uint32_t xt1, uint32_t xt2, + uint32_t yt1, uint32_t yt2, + char *dst, const char *src, + uint32_t dst_pitch, int32_t src_pitch, + bool has_swizzling, + enum isl_tiling tiling, + isl_memcpy_type copy_type); + +/** + * @brief performs a copy from tiled to linear surface + * + */ +void +isl_memcpy_tiled_to_linear(uint32_t xt1, uint32_t xt2, + uint32_t yt1, uint32_t yt2, + char *dst, const char *src, + int32_t dst_pitch, uint32_t src_pitch, + bool has_swizzling, + enum isl_tiling tiling, + isl_memcpy_type copy_type); + #ifdef __cplusplus } #endif