X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fintel%2Fisl%2Fisl_gen7.c;h=fa2456679684c4f9bd7d3ce3b9bf4086c0c64cfb;hb=272ab2823d17173203f2f03c85c95acdcd7d1226;hp=ab47a7f62292ae7cb3a501f95bc0f78f215469a4;hpb=df9bb8dc059a3cdb0a2099deb25cb4292e301933;p=mesa.git

diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
index ab47a7f6229..fa245667968 100644
--- a/src/intel/isl/isl_gen7.c
+++ b/src/intel/isl/isl_gen7.c
@@ -24,6 +24,27 @@
 #include "isl_gen7.h"
 #include "isl_priv.h"
 
+static bool
+gen7_format_needs_valign2(const struct isl_device *dev,
+                          enum isl_format format)
+{
+   assert(ISL_DEV_GEN(dev) == 7);
+
+   /* From the Ivybridge PRM (2012-05-31), Volume 4, Part 1, Section 2.12.1,
+    * RENDER_SURFACE_STATE Surface Vertical Alignment:
+    *
+    *    - Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL
+    *      (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY
+    *      (0x190)
+    *
+    *    - VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
+    *
+    * The R32G32B32_FLOAT restriction is dropped on Haswell.
+    */
+   return isl_format_is_yuv(format) ||
+          (format == ISL_FORMAT_R32G32B32_FLOAT && !ISL_DEV_IS_HASWELL(dev));
+}
+
 bool
 isl_gen7_choose_msaa_layout(const struct isl_device *dev,
                             const struct isl_surf_init_info *info,
@@ -81,6 +102,10 @@ isl_gen7_choose_msaa_layout(const struct isl_device *dev,
     * surfaces with RGBA8I, RGBA16I and RGBA32I.
     */
 
+   /* Multisampling requires vertical alignment of four. */
+   if (info->samples > 1 && gen7_format_needs_valign2(dev, info->format))
+      return false;
+
    /* More obvious restrictions */
    if (isl_surf_usage_is_display(info->usage))
       return false;
@@ -109,7 +134,7 @@ isl_gen7_choose_msaa_layout(const struct isl_device *dev,
     *    is >= 8192 (meaning the actual surface width is >= 8193 pixels), this
     *    field must be set to MSFMT_MSS.
     */
-   if (info->samples == 8 && info->width == 8192)
+   if (info->samples == 8 && info->width > 8192)
       require_array = true;
 
    /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
@@ -152,25 +177,6 @@ isl_gen7_choose_msaa_layout(const struct isl_device *dev,
    return true;
 }
 
-static bool
-gen7_format_needs_valign2(const struct isl_device *dev,
-                          enum isl_format format)
-{
-   assert(ISL_DEV_GEN(dev) == 7);
-
-   /* From the Ivybridge PRM (2012-05-31), Volume 4, Part 1, Section 2.12.1,
-    * RENDER_SURFACE_STATE Surface Vertical Alignment:
-    *
-    *    - Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL
-    *      (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY
-    *      (0x190)
-    *
-    *    - VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
-    */
-   return isl_format_is_yuv(format) ||
-          format == ISL_FORMAT_R32G32B32_FLOAT;
-}
-
 /**
  * @brief Filter out tiling flags that are incompatible with the surface.
  *
@@ -207,11 +213,14 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
       *flags &= ISL_TILING_ANY_Y_MASK;
    }
 
-   /* Separate stencil requires W tiling, and W tiling requires separate
-    * stencil.
-    */
    if (isl_surf_usage_is_stencil(info->usage)) {
-      *flags &= ISL_TILING_W_BIT;
+      if (ISL_DEV_GEN(dev) >= 12) {
+         /* Stencil requires Y. */
+         *flags &= ISL_TILING_ANY_Y_MASK;
+      } else {
+         /* Stencil requires W. */
+         *flags &= ISL_TILING_W_BIT;
+      }
    } else {
       *flags &= ~ISL_TILING_W_BIT;
    }
@@ -242,9 +251,19 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
    }
 
    if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT) {
-      /* Before Skylake, the display engine does not accept Y */
-      /* FINISHME[SKL]: Y tiling for display surfaces */
-      *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT);
+      if (ISL_DEV_GEN(dev) >= 12) {
+         *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT |
+                    ISL_TILING_Y0_BIT);
+      } else if (ISL_DEV_GEN(dev) >= 9) {
+         /* Note we let Yf even though it was cleared above. This is just for
+          * completeness.
+          */
+         *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT |
+                    ISL_TILING_Y0_BIT | ISL_TILING_Yf_BIT);
+      } else {
+         /* Before Skylake, the display engine does not accept Y */
+         *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT);
+      }
    }
 
    if (info->samples > 1) {
@@ -288,6 +307,29 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
     */
    if (ISL_DEV_GEN(dev) < 7 && isl_format_get_layout(info->format)->bpb >= 128)
       *flags &= ~ISL_TILING_Y0_BIT;
+
+   /* From the BDW and SKL PRMs, Volume 2d,
+    * RENDER_SURFACE_STATE::Width - Programming Notes:
+    *
+    *   A known issue exists if a primitive is rendered to the first 2 rows and
+    *   last 2 columns of a 16K width surface. If any geometry is drawn inside
+    *   this square it will be copied to column X=2 and X=3 (arrangement on Y
+    *   position will stay the same). If any geometry exceeds the boundaries of
+    *   this 2x2 region it will be drawn normally. The issue also only occurs
+    *   if the surface has TileMode != Linear.
+    *
+    * [Internal documentation notes that this issue isn't present on SKL GT4.]
+    * To prevent this rendering corruption, only allow linear tiling for
+    * surfaces with widths greater than 16K-2 pixels.
+    *
+    * TODO: Is this an issue for multisampled surfaces as well?
+    */
+   if (info->width > 16382 && info->samples == 1 &&
+       info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT &&
+       (ISL_DEV_GEN(dev) == 8 ||
+        (dev->info->is_skylake && dev->info->gt != 4))) {
+          *flags &= ISL_TILING_LINEAR_BIT;
+   }
 }
 
 void