X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fintel%2Fisl%2Fisl_surface_state.c;h=e44d5f74137c0a00c173bcefab93bedcfa0019f3;hb=c4bfa6dfbb15e34171f31854c04cb8abcfdba01b;hp=d63b245ef23a54d1f9d3ddf1c9f0d38bcf5689a6;hpb=332a5d7a3f28f1c8b1231959085f1421e5c0c535;p=mesa.git diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index d63b245ef23..e44d5f74137 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -26,8 +26,10 @@ #define __gen_address_type uint64_t #define __gen_user_data void -static inline uint64_t -__gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta) +static uint64_t +__gen_combine_address(__attribute__((unused)) void *data, + __attribute__((unused)) void *loc, uint64_t addr, + uint32_t delta) { return addr + delta; } @@ -37,10 +39,6 @@ __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta) #include "isl_priv.h" -#define __PASTE2(x, y) x ## y -#define __PASTE(x, y) __PASTE2(x, y) -#define isl_genX(x) __PASTE(isl_, genX(x)) - #if GEN_GEN >= 8 static const uint8_t isl_to_gen_halign[] = { [4] = HALIGN4, @@ -74,7 +72,9 @@ static const uint8_t isl_to_gen_tiling[] = { [ISL_TILING_Y0] = YMAJOR, [ISL_TILING_Yf] = YMAJOR, [ISL_TILING_Ys] = YMAJOR, +#if GEN_GEN <= 11 [ISL_TILING_W] = WMAJOR, +#endif }; #endif @@ -86,7 +86,17 @@ static const uint32_t isl_to_gen_multisample_layout[] = { }; #endif -#if GEN_GEN >= 9 +#if GEN_GEN >= 12 +static const uint32_t isl_to_gen_aux_mode[] = { + [ISL_AUX_USAGE_NONE] = AUX_NONE, + [ISL_AUX_USAGE_MCS] = AUX_CCS_E, + [ISL_AUX_USAGE_GEN12_CCS_E] = AUX_CCS_E, + [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E, + [ISL_AUX_USAGE_HIZ_CCS_WT] = AUX_CCS_E, + [ISL_AUX_USAGE_MCS_CCS] = AUX_MCS_LCE, + [ISL_AUX_USAGE_STC_CCS] = AUX_CCS_E, +}; +#elif GEN_GEN >= 9 static const uint32_t isl_to_gen_aux_mode[] = { [ISL_AUX_USAGE_NONE] = AUX_NONE, [ISL_AUX_USAGE_HIZ] = AUX_HIZ, @@ -134,7 +144,7 @@ get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage) * hardware. Note that this does NOT give you the actual hardware enum values * but an index into the isl_to_gen_[hv]align arrays above. */ -static inline struct isl_extent3d +UNUSED static struct isl_extent3d get_image_alignment(const struct isl_surf *surf) { if (GEN_GEN >= 9) { @@ -254,8 +264,59 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, if (info->surf->dim == ISL_SURF_DIM_1D) assert(!isl_format_is_compressed(info->view->format)); + if (isl_format_is_compressed(info->surf->format)) { + /* You're not allowed to make a view of a compressed format with any + * format other than the surface format. None of the userspace APIs + * allow for this directly and doing so would mess up a number of + * surface parameters such as Width, Height, and alignments. Ideally, + * we'd like to assert that the two formats match. However, we have an + * S3TC workaround that requires us to do reinterpretation. So assert + * that they're at least the same bpb and block size. + */ + ASSERTED const struct isl_format_layout *surf_fmtl = + isl_format_get_layout(info->surf->format); + ASSERTED const struct isl_format_layout *view_fmtl = + isl_format_get_layout(info->surf->format); + assert(surf_fmtl->bpb == view_fmtl->bpb); + assert(surf_fmtl->bw == view_fmtl->bw); + assert(surf_fmtl->bh == view_fmtl->bh); + } + s.SurfaceFormat = info->view->format; +#if GEN_GEN >= 12 + /* The BSpec description of this field says: + * + * "This bit field, when set, indicates if the resource is created as + * Depth/Stencil resource." + * + * "SW must set this bit for any resource that was created with + * Depth/Stencil resource flag. Setting this bit allows HW to properly + * interpret the data-layout for various cases. For any resource that's + * created without Depth/Stencil resource flag, it must be reset." + * + * Even though the docs for this bit seem to imply that it's required for + * anything which might have been used for depth/stencil, empirical + * evidence suggests that it only affects CCS compression usage. There are + * a few things which back this up: + * + * 1. The docs are also pretty clear that this bit was added as part + * of enabling Gen12 depth/stencil lossless compression. + * + * 2. The only new difference between depth/stencil and color images on + * Gen12 (where the bit was added) is how they treat CCS compression. + * All other differences such as alignment requirements and MSAA layout + * are already covered by other bits. + * + * Under these assumptions, it makes sense for ISL to model this bit as + * being an extension of AuxiliarySurfaceMode where STC_CCS and HIZ_CCS_WT + * are indicated by AuxiliarySurfaceMode == CCS_E and DepthStencilResource + * == true. + */ + s.DepthStencilResource = info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT || + info->aux_usage == ISL_AUX_USAGE_STC_CCS; +#endif + #if GEN_GEN <= 5 s.ColorBufferComponentWriteDisables = info->write_disables; #else @@ -263,7 +324,8 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, #endif #if GEN_IS_HASWELL - s.IntegerSurfaceFormat = isl_format_has_int_channel(s.SurfaceFormat); + s.IntegerSurfaceFormat = + isl_format_has_int_channel((enum isl_format) s.SurfaceFormat); #endif assert(info->surf->logical_level0_px.width > 0 && @@ -371,7 +433,11 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, unreachable("bad SurfaceType"); } -#if GEN_GEN >= 7 +#if GEN_GEN >= 12 + /* GEN:BUG:1806565034: Only set SurfaceArray if arrayed surface is > 1. */ + s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D && + info->view->array_len > 1; +#elif GEN_GEN >= 7 s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D; #endif @@ -413,7 +479,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, /* For gen9 1-D textures, surface pitch is ignored */ s.SurfacePitch = 0; } else { - s.SurfacePitch = info->surf->row_pitch - 1; + s.SurfacePitch = info->surf->row_pitch_B - 1; } #if GEN_GEN >= 8 @@ -424,6 +490,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, #endif #if GEN_GEN >= 8 + assert(GEN_GEN < 12 || info->surf->tiling != ISL_TILING_W); s.TileMode = isl_to_gen_tiling[info->surf->tiling]; #else s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR, @@ -437,18 +504,21 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, s.RenderCacheReadWriteMode = 0; #endif - if (info->view->usage & ISL_SURF_USAGE_CUBE_BIT) { -#if GEN_GEN >= 8 - s.CubeFaceEnablePositiveZ = 1; - s.CubeFaceEnableNegativeZ = 1; - s.CubeFaceEnablePositiveY = 1; - s.CubeFaceEnableNegativeY = 1; - s.CubeFaceEnablePositiveX = 1; - s.CubeFaceEnableNegativeX = 1; -#else - s.CubeFaceEnables = 0x3f; +#if GEN_GEN >= 11 + /* We've seen dEQP failures when enabling this bit with UINT formats, + * which particularly affects blorp_copy() operations. It shouldn't + * have any effect on UINT textures anyway, so disable it for them. + */ + s.EnableUnormPathInColorPipe = + !isl_format_has_int_channel(info->view->format); #endif - } + + s.CubeFaceEnablePositiveZ = 1; + s.CubeFaceEnableNegativeZ = 1; + s.CubeFaceEnablePositiveY = 1; + s.CubeFaceEnableNegativeY = 1; + s.CubeFaceEnablePositiveX = 1; + s.CubeFaceEnableNegativeX = 1; #if GEN_GEN >= 6 s.NumberofMultisamples = ffs(info->surf->samples) - 1; @@ -459,42 +529,15 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, #endif #if (GEN_GEN >= 8 || GEN_IS_HASWELL) - if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) { - /* From the Sky Lake PRM Vol. 2d, - * RENDER_SURFACE_STATE::Shader Channel Select Red - * - * "For Render Target, Red, Green and Blue Shader Channel Selects - * MUST be such that only valid components can be swapped i.e. only - * change the order of components in the pixel. Any other values for - * these Shader Channel Select fields are not valid for Render - * Targets. This also means that there MUST not be multiple shader - * channels mapped to the same RT channel." - */ - assert(info->view->swizzle.r == ISL_CHANNEL_SELECT_RED || - info->view->swizzle.r == ISL_CHANNEL_SELECT_GREEN || - info->view->swizzle.r == ISL_CHANNEL_SELECT_BLUE); - assert(info->view->swizzle.g == ISL_CHANNEL_SELECT_RED || - info->view->swizzle.g == ISL_CHANNEL_SELECT_GREEN || - info->view->swizzle.g == ISL_CHANNEL_SELECT_BLUE); - assert(info->view->swizzle.b == ISL_CHANNEL_SELECT_RED || - info->view->swizzle.b == ISL_CHANNEL_SELECT_GREEN || - info->view->swizzle.b == ISL_CHANNEL_SELECT_BLUE); - assert(info->view->swizzle.r != info->view->swizzle.g); - assert(info->view->swizzle.r != info->view->swizzle.b); - assert(info->view->swizzle.g != info->view->swizzle.b); - - /* From the Sky Lake PRM Vol. 2d, - * RENDER_SURFACE_STATE::Shader Channel Select Alpha - * - * "For Render Target, this field MUST be programmed to - * value = SCS_ALPHA." - */ - assert(info->view->swizzle.a == ISL_CHANNEL_SELECT_ALPHA); - } - s.ShaderChannelSelectRed = info->view->swizzle.r; - s.ShaderChannelSelectGreen = info->view->swizzle.g; - s.ShaderChannelSelectBlue = info->view->swizzle.b; - s.ShaderChannelSelectAlpha = info->view->swizzle.a; + if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) + assert(isl_swizzle_supports_rendering(dev->info, info->view->swizzle)); + + s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->view->swizzle.r; + s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->view->swizzle.g; + s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->view->swizzle.b; + s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->view->swizzle.a; +#else + assert(isl_swizzle_is_identity(info->view->swizzle)); #endif s.SurfaceBaseAddress = info->address; @@ -542,32 +585,67 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, #endif #if GEN_GEN >= 7 - if (info->aux_surf && info->aux_usage != ISL_AUX_USAGE_NONE) { + if (info->aux_usage != ISL_AUX_USAGE_NONE) { + /* Check valid aux usages per-gen */ + if (GEN_GEN >= 12) { + assert(info->aux_usage == ISL_AUX_USAGE_MCS || + info->aux_usage == ISL_AUX_USAGE_CCS_E || + info->aux_usage == ISL_AUX_USAGE_GEN12_CCS_E || + info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT || + info->aux_usage == ISL_AUX_USAGE_MCS_CCS || + info->aux_usage == ISL_AUX_USAGE_STC_CCS); + } else if (GEN_GEN >= 9) { + assert(info->aux_usage == ISL_AUX_USAGE_HIZ || + info->aux_usage == ISL_AUX_USAGE_MCS || + info->aux_usage == ISL_AUX_USAGE_CCS_D || + info->aux_usage == ISL_AUX_USAGE_CCS_E); + } else if (GEN_GEN >= 8) { + assert(info->aux_usage == ISL_AUX_USAGE_HIZ || + info->aux_usage == ISL_AUX_USAGE_MCS || + info->aux_usage == ISL_AUX_USAGE_CCS_D); + } else if (GEN_GEN >= 7) { + assert(info->aux_usage == ISL_AUX_USAGE_MCS || + info->aux_usage == ISL_AUX_USAGE_CCS_D); + } + /* The docs don't appear to say anything whatsoever about compression * and the data port. Testing seems to indicate that the data port * completely ignores the AuxiliarySurfaceMode field. + * + * On gen12 HDC supports compression. */ - assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT)); + if (GEN_GEN < 12) + assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT)); - struct isl_tile_info tile_info; - isl_surf_get_tile_info(dev, info->aux_surf, &tile_info); - uint32_t pitch_in_tiles = - info->aux_surf->row_pitch / tile_info.phys_extent_B.width; + if (isl_surf_usage_is_depth(info->surf->usage)) + assert(isl_aux_usage_has_hiz(info->aux_usage)); - s.AuxiliarySurfaceBaseAddress = info->aux_address; - s.AuxiliarySurfacePitch = pitch_in_tiles - 1; - -#if GEN_GEN >= 8 - assert(GEN_GEN >= 9 || info->aux_usage != ISL_AUX_USAGE_CCS_E); - /* Auxiliary surfaces in ISL have compressed formats but the hardware - * doesn't expect our definition of the compression, it expects qpitch - * in units of samples on the main surface. - */ - s.AuxiliarySurfaceQPitch = - isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2; + if (isl_surf_usage_is_stencil(info->surf->usage)) + assert(info->aux_usage == ISL_AUX_USAGE_STC_CCS); - if (info->aux_usage == ISL_AUX_USAGE_HIZ) { - /* The number of samples must be 1 */ + if (isl_aux_usage_has_hiz(info->aux_usage)) { + /* For Gen8-10, there are some restrictions around sampling from HiZ. + * The Skylake PRM docs for RENDER_SURFACE_STATE::AuxiliarySurfaceMode + * say: + * + * "If this field is set to AUX_HIZ, Number of Multisamples must + * be MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D." + * + * On Gen12, the docs are a bit less obvious but the restriction is + * the same. The limitation isn't called out explicitly but the docs + * for the CCS_E value of RENDER_SURFACE_STATE::AuxiliarySurfaceMode + * say: + * + * "If Number of multisamples > 1, programming this value means + * MSAA compression is enabled for that surface. Auxillary surface + * is MSC with tile y." + * + * Since this interpretation ignores whether the surface is + * depth/stencil or not and since multisampled depth buffers use + * ISL_MSAA_LAYOUT_INTERLEAVED which is incompatible with MCS + * compression, this means that we can't even specify MSAA depth CCS + * in RENDER_SURFACE_STATE::AuxiliarySurfaceMode. + */ assert(info->surf->samples == 1); /* The dimension must not be 3D */ @@ -585,16 +663,48 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, } } +#if GEN_GEN >= 8 s.AuxiliarySurfaceMode = isl_to_gen_aux_mode[info->aux_usage]; #else - assert(info->aux_usage == ISL_AUX_USAGE_MCS || - info->aux_usage == ISL_AUX_USAGE_CCS_D); s.MCSEnable = true; #endif } -#endif + + /* The auxiliary buffer info is filled when it's useable by the HW. + * + * Starting with Gen12, the only form of compression that can be used + * with RENDER_SURFACE_STATE which requires an aux surface is MCS. + * HiZ still requires a surface but the HiZ surface can only be + * accessed through 3DSTATE_HIER_DEPTH_BUFFER. + * + * On all earlier hardware, an aux surface is required for all forms + * of compression. + */ + if ((GEN_GEN < 12 && info->aux_usage != ISL_AUX_USAGE_NONE) || + (GEN_GEN >= 12 && isl_aux_usage_has_mcs(info->aux_usage))) { + + assert(info->aux_surf != NULL); + + struct isl_tile_info tile_info; + isl_surf_get_tile_info(info->aux_surf, &tile_info); + uint32_t pitch_in_tiles = + info->aux_surf->row_pitch_B / tile_info.phys_extent_B.width; + + s.AuxiliarySurfaceBaseAddress = info->aux_address; + s.AuxiliarySurfacePitch = pitch_in_tiles - 1; #if GEN_GEN >= 8 + /* Auxiliary surfaces in ISL have compressed formats but the hardware + * doesn't expect our definition of the compression, it expects qpitch + * in units of samples on the main surface. + */ + s.AuxiliarySurfaceQPitch = + isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2; +#endif + } +#endif + +#if GEN_GEN >= 8 && GEN_GEN < 11 /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0 * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes): * @@ -626,11 +736,44 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, #endif if (info->aux_usage != ISL_AUX_USAGE_NONE) { -#if GEN_GEN >= 9 - s.RedClearColor = info->clear_color.u32[0]; - s.GreenClearColor = info->clear_color.u32[1]; - s.BlueClearColor = info->clear_color.u32[2]; - s.AlphaClearColor = info->clear_color.u32[3]; + if (info->use_clear_address) { +#if GEN_GEN >= 10 + s.ClearValueAddressEnable = true; + s.ClearValueAddress = info->clear_address; +#else + unreachable("Gen9 and earlier do not support indirect clear colors"); +#endif + } + +#if GEN_GEN == 11 + /* + * From BXML > GT > Shared Functions > vol5c Shared Functions > + * [Structure] RENDER_SURFACE_STATE [BDW+] > ClearColorConversionEnable: + * + * Project: Gen11 + * + * "Enables Pixel backend hw to convert clear values into native format + * and write back to clear address, so that display and sampler can use + * the converted value for resolving fast cleared RTs." + * + * Summary: + * Clear color conversion must be enabled if the clear color is stored + * indirectly and fast color clears are enabled. + */ + if (info->use_clear_address) { + s.ClearColorConversionEnable = true; + } +#endif + +#if GEN_GEN >= 12 + assert(info->use_clear_address); +#elif GEN_GEN >= 9 + if (!info->use_clear_address) { + s.RedClearColor = info->clear_color.u32[0]; + s.GreenClearColor = info->clear_color.u32[1]; + s.BlueClearColor = info->clear_color.u32[2]; + s.AlphaClearColor = info->clear_color.u32[3]; + } #elif GEN_GEN >= 7 /* Prior to Sky Lake, we only have one bit for the clear color which * gives us 0 or 1 in whatever the surface's format happens to be. @@ -661,10 +804,30 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, } void -isl_genX(buffer_fill_state_s)(void *state, +isl_genX(buffer_fill_state_s)(const struct isl_device *dev, void *state, const struct isl_buffer_fill_state_info *restrict info) { - uint32_t num_elements = info->size / info->stride; + uint64_t buffer_size = info->size_B; + + /* Uniform and Storage buffers need to have surface size not less that the + * aligned 32-bit size of the buffer. To calculate the array lenght on + * unsized arrays in StorageBuffer the last 2 bits store the padding size + * added to the surface, so we can calculate latter the original buffer + * size to know the number of elements. + * + * surface_size = isl_align(buffer_size, 4) + + * (isl_align(buffer_size) - buffer_size) + * + * buffer_size = (surface_size & ~3) - (surface_size & 3) + */ + if (info->format == ISL_FORMAT_RAW || + info->stride_B < isl_format_get_layout(info->format)->bpb / 8) { + assert(info->stride_B == 1); + uint64_t aligned_size = isl_align(buffer_size, 4); + buffer_size = aligned_size + (aligned_size - buffer_size); + } + + uint32_t num_elements = buffer_size / info->stride_B; if (GEN_GEN >= 7) { /* From the IVB PRM, SURFACE_STATE::Height, @@ -707,7 +870,26 @@ isl_genX(buffer_fill_state_s)(void *state, s.Depth = ((num_elements - 1) >> 20) & 0x7f; #endif - s.SurfacePitch = info->stride - 1; + if (GEN_GEN == 12 && dev->info->revision == 0) { + /* TGL-LP A0 has a HW bug (fixed in later HW) which causes buffer + * textures with very close base addresses (delta < 64B) to corrupt each + * other. We can sort-of work around this by making small buffer + * textures 1D textures instead. This doesn't fix the problem for large + * buffer textures but the liklihood of large, overlapping, and very + * close buffer textures is fairly low and the point is to hack around + * the bug so we can run apps and tests. + */ + if (info->format != ISL_FORMAT_RAW && + info->stride_B == isl_format_get_layout(info->format)->bpb / 8 && + num_elements <= (1 << 14)) { + s.SurfaceType = SURFTYPE_1D; + s.Width = num_elements - 1; + s.Height = 0; + s.Depth = 0; + } + } + + s.SurfacePitch = info->stride_B - 1; #if GEN_GEN >= 6 s.NumberofMultisamples = MULTISAMPLECOUNT_1; @@ -731,11 +913,55 @@ isl_genX(buffer_fill_state_s)(void *state, #endif #if (GEN_GEN >= 8 || GEN_IS_HASWELL) - s.ShaderChannelSelectRed = SCS_RED; - s.ShaderChannelSelectGreen = SCS_GREEN; - s.ShaderChannelSelectBlue = SCS_BLUE; - s.ShaderChannelSelectAlpha = SCS_ALPHA; + s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->swizzle.r; + s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->swizzle.g; + s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->swizzle.b; + s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->swizzle.a; #endif GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s); } + +void +isl_genX(null_fill_state)(void *state, struct isl_extent3d size) +{ + struct GENX(RENDER_SURFACE_STATE) s = { + .SurfaceType = SURFTYPE_NULL, + /* We previously had this format set to B8G8R8A8_UNORM but ran into + * hangs on IVB. R32_UINT seems to work for everybody. + * + * https://gitlab.freedesktop.org/mesa/mesa/-/issues/1872 + */ + .SurfaceFormat = ISL_FORMAT_R32_UINT, +#if GEN_GEN >= 7 + .SurfaceArray = size.depth > 1, +#endif +#if GEN_GEN >= 8 + .TileMode = YMAJOR, +#else + .TiledSurface = true, + .TileWalk = TILEWALK_YMAJOR, +#endif +#if GEN_GEN == 7 + /* According to PRMs: "Volume 4 Part 1: Subsystem and Cores – Shared + * Functions" + * + * RENDER_SURFACE_STATE::Surface Vertical Alignment + * + * "This field must be set to VALIGN_4 for all tiled Y Render Target + * surfaces." + * + * Affect IVB, HSW. + */ + .SurfaceVerticalAlignment = VALIGN_4, +#endif + .Width = size.width - 1, + .Height = size.height - 1, + .Depth = size.depth - 1, + .RenderTargetViewExtent = size.depth - 1, +#if GEN_GEN <= 5 + .ColorBufferComponentWriteDisables = 0xf, +#endif + }; + GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s); +}