X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fintel%2Fisl%2Fisl_surface_state.c;h=f181c3dfb2f2a94b96f55c37988e7f148217a4e4;hb=f3c59ca947ed20cf03ce2f0f4970d383b828bf01;hp=f64d96ca0591da8f0d9e0a256372a3856bc0a9d7;hpb=96706bad5ff37e56ee48f9bbb143d39a6e113a62;p=mesa.git diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index f64d96ca059..f181c3dfb2f 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -26,8 +26,10 @@ #define __gen_address_type uint64_t #define __gen_user_data void -static inline uint64_t -__gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta) +static uint64_t +__gen_combine_address(__attribute__((unused)) void *data, + __attribute__((unused)) void *loc, uint64_t addr, + uint32_t delta) { return addr + delta; } @@ -37,10 +39,6 @@ __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta) #include "isl_priv.h" -#define __PASTE2(x, y) x ## y -#define __PASTE(x, y) __PASTE2(x, y) -#define isl_genX(x) __PASTE(isl_, genX(x)) - #if GEN_GEN >= 8 static const uint8_t isl_to_gen_halign[] = { [4] = HALIGN4, @@ -78,11 +76,30 @@ static const uint8_t isl_to_gen_tiling[] = { }; #endif +#if GEN_GEN >= 7 static const uint32_t isl_to_gen_multisample_layout[] = { [ISL_MSAA_LAYOUT_NONE] = MSFMT_MSS, [ISL_MSAA_LAYOUT_INTERLEAVED] = MSFMT_DEPTH_STENCIL, [ISL_MSAA_LAYOUT_ARRAY] = MSFMT_MSS, }; +#endif + +#if GEN_GEN >= 9 +static const uint32_t isl_to_gen_aux_mode[] = { + [ISL_AUX_USAGE_NONE] = AUX_NONE, + [ISL_AUX_USAGE_HIZ] = AUX_HIZ, + [ISL_AUX_USAGE_MCS] = AUX_CCS_D, + [ISL_AUX_USAGE_CCS_D] = AUX_CCS_D, + [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E, +}; +#elif GEN_GEN >= 8 +static const uint32_t isl_to_gen_aux_mode[] = { + [ISL_AUX_USAGE_NONE] = AUX_NONE, + [ISL_AUX_USAGE_HIZ] = AUX_HIZ, + [ISL_AUX_USAGE_MCS] = AUX_MCS, + [ISL_AUX_USAGE_CCS_D] = AUX_MCS, +}; +#endif static uint8_t get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage) @@ -94,12 +111,14 @@ get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage) assert(!(usage & ISL_SURF_USAGE_CUBE_BIT)); return SURFTYPE_1D; case ISL_SURF_DIM_2D: - if (usage & ISL_SURF_USAGE_STORAGE_BIT) { - /* Storage images are always plain 2-D, not cube */ - return SURFTYPE_2D; - } else if (usage & ISL_SURF_USAGE_CUBE_BIT) { + if ((usage & ISL_SURF_USAGE_CUBE_BIT) && + (usage & ISL_SURF_USAGE_TEXTURE_BIT)) { + /* We need SURFTYPE_CUBE to make cube sampling work */ return SURFTYPE_CUBE; } else { + /* Everything else (render and storage) treat cubes as plain + * 2D array textures + */ return SURFTYPE_2D; } case ISL_SURF_DIM_3D: @@ -113,7 +132,7 @@ get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage) * hardware. Note that this does NOT give you the actual hardware enum values * but an index into the isl_to_gen_[hv]align arrays above. */ -static struct isl_extent3d +UNUSED static struct isl_extent3d get_image_alignment(const struct isl_surf *surf) { if (GEN_GEN >= 9) { @@ -123,7 +142,7 @@ get_image_alignment(const struct isl_surf *surf) * true alignment is likely outside the enum range of HALIGN* and * VALIGN*. */ - return isl_extent3d(0, 0, 0); + return isl_extent3d(4, 4, 1); } else { /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units * of surface elements (not pixels nor samples). For compressed formats, @@ -153,9 +172,21 @@ get_qpitch(const struct isl_surf *surf) default: unreachable("Bad isl_surf_dim"); case ISL_DIM_LAYOUT_GEN4_2D: - case ISL_DIM_LAYOUT_GEN4_3D: if (GEN_GEN >= 9) { - return isl_surf_get_array_pitch_el_rows(surf); + if (surf->dim == ISL_SURF_DIM_3D && surf->tiling == ISL_TILING_W) { + /* This is rather annoying and completely undocumented. It + * appears that the hardware has a bug (or undocumented feature) + * regarding stencil buffers most likely related to the way + * W-tiling is handled as modified Y-tiling. If you bind a 3-D + * stencil buffer normally, and use texelFetch on it, the z or + * array index will get implicitly multiplied by 2 for no obvious + * reason. The fix appears to be to divide qpitch by 2 for + * W-tiled surfaces. + */ + return isl_surf_get_array_pitch_el_rows(surf) / 2; + } else { + return isl_surf_get_array_pitch_el_rows(surf); + } } else { /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch * @@ -180,6 +211,22 @@ get_qpitch(const struct isl_surf *surf) * slices. */ return isl_surf_get_array_pitch_el(surf); + case ISL_DIM_LAYOUT_GEN4_3D: + /* QPitch doesn't make sense for ISL_DIM_LAYOUT_GEN4_3D since it uses a + * different pitch at each LOD. Also, the QPitch field is ignored for + * these surfaces. From the Broadwell PRM documentation for QPitch: + * + * This field specifies the distance in rows between array slices. It + * is used only in the following cases: + * - Surface Array is enabled OR + * - Number of Mulitsamples is not NUMSAMPLES_1 and Multisampled + * Surface Storage Format set to MSFMT_MSS OR + * - Surface Type is SURFTYPE_CUBE + * + * None of the three conditions above can possibly apply to a 3D surface + * so it is safe to just set QPitch to 0. + */ + return 0; } } #endif /* GEN_GEN >= 8 */ @@ -192,23 +239,89 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, s.SurfaceType = get_surftype(info->surf->dim, info->view->usage); - if (info->view->usage & ISL_SURF_USAGE_STORAGE_BIT) { - s.SurfaceFormat = - isl_lower_storage_image_format(dev->info, info->view->format); - } else { - s.SurfaceFormat = info->view->format; + if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) + assert(isl_format_supports_rendering(dev->info, info->view->format)); + else if (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) + assert(isl_format_supports_sampling(dev->info, info->view->format)); + + /* From the Sky Lake PRM Vol. 2d, RENDER_SURFACE_STATE::SurfaceFormat + * + * This field cannot be a compressed (BC*, DXT*, FXT*, ETC*, EAC*) + * format if the Surface Type is SURFTYPE_1D + */ + if (info->surf->dim == ISL_SURF_DIM_1D) + assert(!isl_format_is_compressed(info->view->format)); + + if (isl_format_is_compressed(info->surf->format)) { + /* You're not allowed to make a view of a compressed format with any + * format other than the surface format. None of the userspace APIs + * allow for this directly and doing so would mess up a number of + * surface parameters such as Width, Height, and alignments. Ideally, + * we'd like to assert that the two formats match. However, we have an + * S3TC workaround that requires us to do reinterpretation. So assert + * that they're at least the same bpb and block size. + */ + MAYBE_UNUSED const struct isl_format_layout *surf_fmtl = + isl_format_get_layout(info->surf->format); + MAYBE_UNUSED const struct isl_format_layout *view_fmtl = + isl_format_get_layout(info->surf->format); + assert(surf_fmtl->bpb == view_fmtl->bpb); + assert(surf_fmtl->bw == view_fmtl->bw); + assert(surf_fmtl->bh == view_fmtl->bh); } + s.SurfaceFormat = info->view->format; + +#if GEN_GEN <= 5 + s.ColorBufferComponentWriteDisables = info->write_disables; +#else + assert(info->write_disables == 0); +#endif + #if GEN_IS_HASWELL - s.IntegerSurfaceFormat = isl_format_has_int_channel(s.SurfaceFormat); + s.IntegerSurfaceFormat = + isl_format_has_int_channel((enum isl_format) s.SurfaceFormat); #endif + assert(info->surf->logical_level0_px.width > 0 && + info->surf->logical_level0_px.height > 0); + s.Width = info->surf->logical_level0_px.width - 1; s.Height = info->surf->logical_level0_px.height - 1; + /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1 + * (Surface Arrays For all surfaces other than separate stencil buffer): + * + * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value + * calculated in the equation above , for every other odd Surface Height + * starting from 1 i.e. 1,5,9,13" + * + * Since this Qpitch errata only impacts the sampler, we have to adjust the + * input for the rendering surface to achieve the same qpitch. For the + * affected heights, we increment the height by 1 for the rendering + * surface. + */ + if (GEN_GEN == 6 && (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) && + info->surf->samples > 1 && + (info->surf->logical_level0_px.height % 4) == 1) + s.Height++; + switch (s.SurfaceType) { case SURFTYPE_1D: case SURFTYPE_2D: + /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement: + * + * "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field + * must be set to zero if this surface is used with sampling engine + * messages." + * + * This restriction appears to exist only on Ivy Bridge. + */ + if (GEN_GEN == 7 && !GEN_IS_HASWELL && !ISL_DEV_IS_BAYTRAIL(dev) && + (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) && + info->surf->samples > 1) + assert(info->view->base_array_layer == 0); + s.MinimumArrayElement = info->view->base_array_layer; /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth: @@ -240,8 +353,6 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, s.RenderTargetViewExtent = s.Depth; break; case SURFTYPE_3D: - s.MinimumArrayElement = info->view->base_array_layer; - /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth: * * If the volume texture is MIP-mapped, this field specifies the @@ -261,18 +372,25 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, * textures with more levels than we can render to. In order to prevent * assert-failures in the packing function below, we only set the field * when it's actually going to be used by the hardware. + * + * Similaraly, the MinimumArrayElement field is ignored by all hardware + * prior to Sky Lake when texturing and we want it set to 0 anyway. + * Since it's already initialized to 0, we can just leave it alone for + * texture surfaces. */ if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT | ISL_SURF_USAGE_STORAGE_BIT)) { - s.RenderTargetViewExtent = isl_minify(info->surf->logical_level0_px.depth, - info->view->base_level) - 1; + s.MinimumArrayElement = info->view->base_array_layer; + s.RenderTargetViewExtent = info->view->array_len - 1; } break; default: unreachable("bad SurfaceType"); } +#if GEN_GEN >= 7 s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D; +#endif if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) { /* For render target surfaces, the hardware interprets field @@ -300,19 +418,17 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, s.MipTailStartLOD = 15; #endif +#if GEN_GEN >= 6 const struct isl_extent3d image_align = get_image_alignment(info->surf); s.SurfaceVerticalAlignment = isl_to_gen_valign[image_align.height]; +#if GEN_GEN >= 7 s.SurfaceHorizontalAlignment = isl_to_gen_halign[image_align.width]; +#endif +#endif - if (info->surf->tiling == ISL_TILING_W) { - /* From the Broadwell PRM documentation for this field: - * - * "If the surface is a stencil buffer (and thus has Tile Mode set - * to TILEMODE_WMAJOR), the pitch must be set to 2x the value - * computed based on width, as the stencil buffer is stored with - * two rows interleaved." - */ - s.SurfacePitch = info->surf->row_pitch * 2 - 1; + if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) { + /* For gen9 1-D textures, surface pitch is ignored */ + s.SurfacePitch = 0; } else { s.SurfacePitch = info->surf->row_pitch - 1; } @@ -328,8 +444,8 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, s.TileMode = isl_to_gen_tiling[info->surf->tiling]; #else s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR, - s.TileWalk = info->surf->tiling == ISL_TILING_X ? TILEWALK_XMAJOR : - TILEWALK_YMAJOR; + s.TileWalk = info->surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR : + TILEWALK_XMAJOR, #endif #if GEN_GEN >= 8 @@ -338,37 +454,128 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, s.RenderCacheReadWriteMode = 0; #endif - if (info->view->usage & ISL_SURF_USAGE_CUBE_BIT) { -#if GEN_GEN >= 8 - s.CubeFaceEnablePositiveZ = 1; - s.CubeFaceEnableNegativeZ = 1; - s.CubeFaceEnablePositiveY = 1; - s.CubeFaceEnableNegativeY = 1; - s.CubeFaceEnablePositiveX = 1; - s.CubeFaceEnableNegativeX = 1; -#else - s.CubeFaceEnables = 0x3f; -#endif - } + s.CubeFaceEnablePositiveZ = 1; + s.CubeFaceEnableNegativeZ = 1; + s.CubeFaceEnablePositiveY = 1; + s.CubeFaceEnableNegativeY = 1; + s.CubeFaceEnablePositiveX = 1; + s.CubeFaceEnableNegativeX = 1; +#if GEN_GEN >= 6 + s.NumberofMultisamples = ffs(info->surf->samples) - 1; +#if GEN_GEN >= 7 s.MultisampledSurfaceStorageFormat = isl_to_gen_multisample_layout[info->surf->msaa_layout]; - s.NumberofMultisamples = ffs(info->surf->samples) - 1; +#endif +#endif #if (GEN_GEN >= 8 || GEN_IS_HASWELL) - s.ShaderChannelSelectRed = info->view->channel_select[0]; - s.ShaderChannelSelectGreen = info->view->channel_select[1]; - s.ShaderChannelSelectBlue = info->view->channel_select[2]; - s.ShaderChannelSelectAlpha = info->view->channel_select[3]; + if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) + assert(isl_swizzle_supports_rendering(dev->info, info->view->swizzle)); + + s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->view->swizzle.r; + s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->view->swizzle.g; + s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->view->swizzle.b; + s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->view->swizzle.a; +#else + assert(isl_swizzle_is_identity(info->view->swizzle)); #endif s.SurfaceBaseAddress = info->address; + +#if GEN_GEN >= 6 s.MOCS = info->mocs; +#endif + +#if GEN_GEN > 4 || GEN_IS_G4X + if (info->x_offset_sa != 0 || info->y_offset_sa != 0) { + /* There are fairly strict rules about when the offsets can be used. + * These are mostly taken from the Sky Lake PRM documentation for + * RENDER_SURFACE_STATE. + */ + assert(info->surf->tiling != ISL_TILING_LINEAR); + assert(info->surf->dim == ISL_SURF_DIM_2D); + assert(isl_is_pow2(isl_format_get_layout(info->view->format)->bpb)); + assert(info->surf->levels == 1); + assert(info->surf->logical_level0_px.array_len == 1); + assert(info->aux_usage == ISL_AUX_USAGE_NONE); + + if (GEN_GEN >= 8) { + /* Broadwell added more rules. */ + assert(info->surf->samples == 1); + if (isl_format_get_layout(info->view->format)->bpb == 8) + assert(info->x_offset_sa % 16 == 0); + if (isl_format_get_layout(info->view->format)->bpb == 16) + assert(info->x_offset_sa % 8 == 0); + } + +#if GEN_GEN >= 7 + s.SurfaceArray = false; +#endif + } + + const unsigned x_div = 4; + const unsigned y_div = GEN_GEN >= 8 ? 4 : 2; + assert(info->x_offset_sa % x_div == 0); + assert(info->y_offset_sa % y_div == 0); + s.XOffset = info->x_offset_sa / x_div; + s.YOffset = info->y_offset_sa / y_div; +#else + assert(info->x_offset_sa == 0); + assert(info->y_offset_sa == 0); +#endif + +#if GEN_GEN >= 7 + if (info->aux_surf && info->aux_usage != ISL_AUX_USAGE_NONE) { + /* The docs don't appear to say anything whatsoever about compression + * and the data port. Testing seems to indicate that the data port + * completely ignores the AuxiliarySurfaceMode field. + */ + assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT)); + + struct isl_tile_info tile_info; + isl_surf_get_tile_info(info->aux_surf, &tile_info); + uint32_t pitch_in_tiles = + info->aux_surf->row_pitch / tile_info.phys_extent_B.width; + + s.AuxiliarySurfaceBaseAddress = info->aux_address; + s.AuxiliarySurfacePitch = pitch_in_tiles - 1; #if GEN_GEN >= 8 - s.AuxiliarySurfaceMode = AUX_NONE; + assert(GEN_GEN >= 9 || info->aux_usage != ISL_AUX_USAGE_CCS_E); + /* Auxiliary surfaces in ISL have compressed formats but the hardware + * doesn't expect our definition of the compression, it expects qpitch + * in units of samples on the main surface. + */ + s.AuxiliarySurfaceQPitch = + isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2; + + if (info->aux_usage == ISL_AUX_USAGE_HIZ) { + /* The number of samples must be 1 */ + assert(info->surf->samples == 1); + + /* The dimension must not be 3D */ + assert(info->surf->dim != ISL_SURF_DIM_3D); + + /* The format must be one of the following: */ + switch (info->view->format) { + case ISL_FORMAT_R32_FLOAT: + case ISL_FORMAT_R24_UNORM_X8_TYPELESS: + case ISL_FORMAT_R16_UNORM: + break; + default: + assert(!"Incompatible HiZ Sampling format"); + break; + } + } + + s.AuxiliarySurfaceMode = isl_to_gen_aux_mode[info->aux_usage]; #else - s.MCSEnable = false; + assert(info->aux_usage == ISL_AUX_USAGE_MCS || + info->aux_usage == ISL_AUX_USAGE_CCS_D); + s.MCSEnable = true; +#endif + } #endif #if GEN_GEN >= 8 @@ -388,40 +595,61 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, s.SamplerL2BypassModeDisable = true; break; default: + /* From the SKL PRM, Programming Note under Sampler Output Channel + * Mapping: + * + * If a surface has an associated HiZ Auxilliary surface, the + * Sampler L2 Bypass Mode Disable field in the RENDER_SURFACE_STATE + * must be set. + */ + if (GEN_GEN >= 9 && info->aux_usage == ISL_AUX_USAGE_HIZ) + s.SamplerL2BypassModeDisable = true; break; } } #endif + if (info->aux_usage != ISL_AUX_USAGE_NONE) { + if (info->use_clear_address) { +#if GEN_GEN >= 10 + s.ClearValueAddressEnable = true; + s.ClearValueAddress = info->clear_address; +#else + unreachable("Gen9 and earlier do not support indirect clear colors"); +#endif + } #if GEN_GEN >= 9 - s.RedClearColor = info->clear_color.u32[0]; - s.GreenClearColor = info->clear_color.u32[1]; - s.BlueClearColor = info->clear_color.u32[2]; - s.AlphaClearColor = info->clear_color.u32[3]; -#elif GEN_GEN >= 7 - /* Prior to Sky Lake, we only have one bit for the clear color which - * gives us 0 or 1 in whatever the surface's format happens to be. - */ - if (isl_format_has_int_channel(info->view->format)) { - for (unsigned i = 0; i < 4; i++) { - assert(info->clear_color.u32[i] == 0 || - info->clear_color.u32[i] == 1); + if (!info->use_clear_address) { + s.RedClearColor = info->clear_color.u32[0]; + s.GreenClearColor = info->clear_color.u32[1]; + s.BlueClearColor = info->clear_color.u32[2]; + s.AlphaClearColor = info->clear_color.u32[3]; } - s.RedClearColor = info->clear_color.u32[0] != 0; - s.GreenClearColor = info->clear_color.u32[1] != 0; - s.BlueClearColor = info->clear_color.u32[2] != 0; - s.AlphaClearColor = info->clear_color.u32[3] != 0; - } else { - for (unsigned i = 0; i < 4; i++) { - assert(info->clear_color.f32[i] == 0.0f || - info->clear_color.f32[i] == 1.0f); +#elif GEN_GEN >= 7 + /* Prior to Sky Lake, we only have one bit for the clear color which + * gives us 0 or 1 in whatever the surface's format happens to be. + */ + if (isl_format_has_int_channel(info->view->format)) { + for (unsigned i = 0; i < 4; i++) { + assert(info->clear_color.u32[i] == 0 || + info->clear_color.u32[i] == 1); + } + s.RedClearColor = info->clear_color.u32[0] != 0; + s.GreenClearColor = info->clear_color.u32[1] != 0; + s.BlueClearColor = info->clear_color.u32[2] != 0; + s.AlphaClearColor = info->clear_color.u32[3] != 0; + } else { + for (unsigned i = 0; i < 4; i++) { + assert(info->clear_color.f32[i] == 0.0f || + info->clear_color.f32[i] == 1.0f); + } + s.RedClearColor = info->clear_color.f32[0] != 0.0f; + s.GreenClearColor = info->clear_color.f32[1] != 0.0f; + s.BlueClearColor = info->clear_color.f32[2] != 0.0f; + s.AlphaClearColor = info->clear_color.f32[3] != 0.0f; } - s.RedClearColor = info->clear_color.f32[0] != 0.0f; - s.GreenClearColor = info->clear_color.f32[1] != 0.0f; - s.BlueClearColor = info->clear_color.f32[2] != 0.0f; - s.AlphaClearColor = info->clear_color.f32[3] != 0.0f; - } #endif + } GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s); } @@ -430,42 +658,124 @@ void isl_genX(buffer_fill_state_s)(void *state, const struct isl_buffer_fill_state_info *restrict info) { - uint32_t num_elements = info->size / info->stride; - - struct GENX(RENDER_SURFACE_STATE) surface_state = { - .SurfaceType = SURFTYPE_BUFFER, - .SurfaceArray = false, - .SurfaceFormat = info->format, - .SurfaceVerticalAlignment = isl_to_gen_valign[4], - .SurfaceHorizontalAlignment = isl_to_gen_halign[4], - .Height = ((num_elements - 1) >> 7) & 0x3fff, - .Width = (num_elements - 1) & 0x7f, - .Depth = ((num_elements - 1) >> 21) & 0x3f, - .SurfacePitch = info->stride - 1, - .NumberofMultisamples = MULTISAMPLECOUNT_1, + uint64_t buffer_size = info->size; + + /* Uniform and Storage buffers need to have surface size not less that the + * aligned 32-bit size of the buffer. To calculate the array lenght on + * unsized arrays in StorageBuffer the last 2 bits store the padding size + * added to the surface, so we can calculate latter the original buffer + * size to know the number of elements. + * + * surface_size = isl_align(buffer_size, 4) + + * (isl_align(buffer_size) - buffer_size) + * + * buffer_size = (surface_size & ~3) - (surface_size & 3) + */ + if (info->format == ISL_FORMAT_RAW || + info->stride < isl_format_get_layout(info->format)->bpb / 8) { + assert(info->stride == 1); + uint64_t aligned_size = isl_align(buffer_size, 4); + buffer_size = aligned_size + (aligned_size - buffer_size); + } + + uint32_t num_elements = buffer_size / info->stride; + + if (GEN_GEN >= 7) { + /* From the IVB PRM, SURFACE_STATE::Height, + * + * For typed buffer and structured buffer surfaces, the number + * of entries in the buffer ranges from 1 to 2^27. For raw buffer + * surfaces, the number of entries in the buffer is the number of bytes + * which can range from 1 to 2^30. + */ + if (info->format == ISL_FORMAT_RAW) { + assert(num_elements <= (1ull << 30)); + assert(num_elements > 0); + } else { + assert(num_elements <= (1ull << 27)); + } + } else { + assert(num_elements <= (1ull << 27)); + } + + struct GENX(RENDER_SURFACE_STATE) s = { 0, }; + + s.SurfaceType = SURFTYPE_BUFFER; + s.SurfaceFormat = info->format; + +#if GEN_GEN >= 6 + s.SurfaceVerticalAlignment = isl_to_gen_valign[4]; +#if GEN_GEN >= 7 + s.SurfaceHorizontalAlignment = isl_to_gen_halign[4]; + s.SurfaceArray = false; +#endif +#endif + +#if GEN_GEN >= 7 + s.Height = ((num_elements - 1) >> 7) & 0x3fff; + s.Width = (num_elements - 1) & 0x7f; + s.Depth = ((num_elements - 1) >> 21) & 0x3ff; +#else + s.Height = ((num_elements - 1) >> 7) & 0x1fff; + s.Width = (num_elements - 1) & 0x7f; + s.Depth = ((num_elements - 1) >> 20) & 0x7f; +#endif + + s.SurfacePitch = info->stride - 1; + +#if GEN_GEN >= 6 + s.NumberofMultisamples = MULTISAMPLECOUNT_1; +#endif #if (GEN_GEN >= 8) - .TileMode = LINEAR, + s.TileMode = LINEAR; #else - .TiledSurface = false, + s.TiledSurface = false; #endif #if (GEN_GEN >= 8) - .RenderCacheReadWriteMode = WriteOnlyCache, + s.RenderCacheReadWriteMode = WriteOnlyCache; #else - .RenderCacheReadWriteMode = 0, + s.RenderCacheReadWriteMode = 0; #endif - .MOCS = info->mocs, + s.SurfaceBaseAddress = info->address; +#if GEN_GEN >= 6 + s.MOCS = info->mocs; +#endif #if (GEN_GEN >= 8 || GEN_IS_HASWELL) - .ShaderChannelSelectRed = SCS_RED, - .ShaderChannelSelectGreen = SCS_GREEN, - .ShaderChannelSelectBlue = SCS_BLUE, - .ShaderChannelSelectAlpha = SCS_ALPHA, + s.ShaderChannelSelectRed = SCS_RED; + s.ShaderChannelSelectGreen = SCS_GREEN; + s.ShaderChannelSelectBlue = SCS_BLUE; + s.ShaderChannelSelectAlpha = SCS_ALPHA; #endif - .SurfaceBaseAddress = info->address, - }; - GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &surface_state); + GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s); +} + +void +isl_genX(null_fill_state)(void *state, struct isl_extent3d size) +{ + struct GENX(RENDER_SURFACE_STATE) s = { + .SurfaceType = SURFTYPE_NULL, + .SurfaceFormat = ISL_FORMAT_B8G8R8A8_UNORM, +#if GEN_GEN >= 7 + .SurfaceArray = size.depth > 0, +#endif +#if GEN_GEN >= 8 + .TileMode = YMAJOR, +#else + .TiledSurface = true, + .TileWalk = TILEWALK_YMAJOR, +#endif + .Width = size.width - 1, + .Height = size.height - 1, + .Depth = size.depth - 1, + .RenderTargetViewExtent = size.depth - 1, +#if GEN_GEN <= 5 + .ColorBufferComponentWriteDisables = 0xf, +#endif + }; + GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s); }