X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fintel%2Ftools%2Fi965_gram.y;h=03ebc7e3e6da750ddf2ec9ebef8bf0983280279d;hb=363e5ef5a5d43c0c59dbbdb3740f6bcadfb95a89;hp=55eaabc154d9cce5be718ee81e74e61c992b508d;hpb=9feb6302f93a3c4192f6eaaf8651154d419ff4ca;p=mesa.git diff --git a/src/intel/tools/i965_gram.y b/src/intel/tools/i965_gram.y index 55eaabc154d..03ebc7e3e6d 100644 --- a/src/intel/tools/i965_gram.y +++ b/src/intel/tools/i965_gram.y @@ -321,6 +321,7 @@ i965_asm_set_dst_nr(struct brw_codegen *p, int integer; unsigned long long int llint; struct brw_reg reg; + enum brw_reg_type reg_type; struct brw_codegen *program; struct predicate predicate; struct condition condition; @@ -466,11 +467,10 @@ i965_asm_set_dst_nr(struct brw_codegen *p, /* writemask */ %type writemask_x writemask_y writemask_z writemask_w -%type writemask +%type writemask /* dst operand */ -%type dst dstoperand dstoperandex dstoperandex_typed dstreg dsttype -%type dstoperandex_ud_typed +%type dst dstoperand dstoperandex dstoperandex_typed dstreg %type dstregion %type saturate relativelocation rellocation @@ -478,16 +478,20 @@ i965_asm_set_dst_nr(struct brw_codegen *p, /* src operand */ %type directsrcoperand directsrcaccoperand indirectsrcoperand srcacc -%type srcarcoperandex srcaccimm srcarcoperandex_typed srctype srcimm -%type srcarcoperandex_ud_typed srcimmtype indirectgenreg indirectregion +%type srcarcoperandex srcaccimm srcarcoperandex_typed srcimm +%type indirectgenreg indirectregion %type immreg src reg32 payload directgenreg_list addrparam region -%type region_wh swizzle directgenreg directmsgreg indirectmsgreg +%type region_wh directgenreg directmsgreg indirectmsgreg +%type swizzle /* registers */ %type accreg addrreg channelenablereg controlreg flagreg ipreg %type notifyreg nullreg performancereg threadcontrolreg statereg maskreg %type subregnum +/* register types */ +%type reg_type imm_type + /* immediate values */ %type immval @@ -775,7 +779,6 @@ binaryaccinstruction: if (p->devinfo->gen >= 7) brw_inst_set_nib_control(p->devinfo, brw_last_inst, $9.nib_ctrl); - } ; @@ -1420,55 +1423,40 @@ dst: ; dstoperand: - dstreg dstregion writemask dsttype + dstreg dstregion writemask reg_type { $$ = $1; - - if ($2 == -1) { - $$.hstride = BRW_HORIZONTAL_STRIDE_1; - $$.vstride = BRW_VERTICAL_STRIDE_1; - $$.width = BRW_WIDTH_1; - } else { - $$.hstride = $2; - } - $$.type = $4.type; - $$.writemask = $3.writemask; + $$.vstride = BRW_VERTICAL_STRIDE_1; + $$.width = BRW_WIDTH_1; + $$.hstride = $2; + $$.type = $4; + $$.writemask = $3; $$.swizzle = BRW_SWIZZLE_NOOP; - $$.subnr = $$.subnr * brw_reg_type_to_size($4.type); + $$.subnr = $$.subnr * brw_reg_type_to_size($4); } ; dstoperandex: - dstoperandex_typed dstregion writemask dsttype + dstoperandex_typed dstregion writemask reg_type { $$ = $1; $$.hstride = $2; - $$.type = $4.type; - $$.writemask = $3.writemask; - $$.subnr = $$.subnr * brw_reg_type_to_size($4.type); - } - | dstoperandex_ud_typed - { - $$ = $1; - $$.hstride = 1; - $$.type = BRW_REGISTER_TYPE_UD; + $$.type = $4; + $$.writemask = $3; + $$.subnr = $$.subnr * brw_reg_type_to_size($4); } /* BSpec says "When the conditional modifier is present, updates * to the selected flag register also occur. In this case, the * register region fields of the ‘null’ operand are valid." */ - | nullreg dstregion writemask dsttype + | nullreg dstregion writemask reg_type { $$ = $1; - if ($2 == -1) { - $$.hstride = BRW_HORIZONTAL_STRIDE_1; - $$.vstride = BRW_VERTICAL_STRIDE_1; - $$.width = BRW_WIDTH_1; - } else { - $$.hstride = $2; - } - $$.writemask = $3.writemask; - $$.type = $4.type; + $$.vstride = BRW_VERTICAL_STRIDE_1; + $$.width = BRW_WIDTH_1; + $$.hstride = $2; + $$.writemask = $3; + $$.type = $4; } | threadcontrolreg { @@ -1478,18 +1466,15 @@ dstoperandex: } ; -dstoperandex_ud_typed: - controlreg - | ipreg - | channelenablereg - | performancereg - ; - dstoperandex_typed: accreg - | flagreg | addrreg + | channelenablereg + | controlreg + | flagreg + | ipreg | maskreg + | performancereg | statereg ; @@ -1523,30 +1508,25 @@ srcaccimm: ; immreg: - immval srcimmtype + immval imm_type { - uint32_t u32; - uint64_t u64; - switch ($2.type) { + switch ($2) { case BRW_REGISTER_TYPE_UD: - u32 = $1; - $$ = brw_imm_ud(u32); + $$ = brw_imm_ud($1); break; case BRW_REGISTER_TYPE_D: $$ = brw_imm_d($1); break; case BRW_REGISTER_TYPE_UW: - u32 = $1 | ($1 << 16); - $$ = brw_imm_uw(u32); + $$ = brw_imm_uw($1 | ($1 << 16)); break; case BRW_REGISTER_TYPE_W: - u32 = $1; - $$ = brw_imm_w(u32); + $$ = brw_imm_w($1); break; case BRW_REGISTER_TYPE_F: $$ = brw_imm_reg(BRW_REGISTER_TYPE_F); + /* Set u64 instead of ud since DIM uses a 64-bit F-typed imm */ $$.u64 = $1; - $$.ud = $1; break; case BRW_REGISTER_TYPE_V: $$ = brw_imm_v($1); @@ -1555,32 +1535,29 @@ immreg: $$ = brw_imm_uv($1); break; case BRW_REGISTER_TYPE_VF: - $$ = brw_imm_reg(BRW_REGISTER_TYPE_VF); - $$.d = $1; + $$ = brw_imm_vf($1); break; case BRW_REGISTER_TYPE_Q: - u64 = $1; - $$ = brw_imm_q(u64); + $$ = brw_imm_q($1); break; case BRW_REGISTER_TYPE_UQ: - u64 = $1; - $$ = brw_imm_uq(u64); + $$ = brw_imm_uq($1); break; case BRW_REGISTER_TYPE_DF: $$ = brw_imm_reg(BRW_REGISTER_TYPE_DF); $$.d64 = $1; break; default: - error(&@2, "Unkown immdediate type %s\n", - brw_reg_type_to_letters($2.type)); + error(&@2, "Unknown immediate type %s\n", + brw_reg_type_to_letters($2)); } } ; reg32: - directgenreg region srctype + directgenreg region reg_type { - $$ = set_direct_src_operand(&$1, $3.type); + $$ = set_direct_src_operand(&$1, $3); $$ = stride($$, $2.vstride, $2.width, $2.hstride); } ; @@ -1607,9 +1584,9 @@ srcimm: directsrcaccoperand: directsrcoperand - | accreg region srctype + | accreg region reg_type { - $$ = set_direct_src_operand(&$1, $3.type); + $$ = set_direct_src_operand(&$1, $3); $$.vstride = $2.vstride; $$.width = $2.width; $$.hstride = $2.hstride; @@ -1617,27 +1594,23 @@ directsrcaccoperand: ; srcarcoperandex: - srcarcoperandex_typed region srctype + srcarcoperandex_typed region reg_type { $$ = brw_reg($1.file, $1.nr, $1.subnr, 0, 0, - $3.type, + $3, $2.vstride, $2.width, $2.hstride, BRW_SWIZZLE_NOOP, WRITEMASK_XYZW); } - | srcarcoperandex_ud_typed - { - $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UD); - } - | nullreg region srctype + | nullreg region reg_type { - $$ = set_direct_src_operand(&$1, $3.type); + $$ = set_direct_src_operand(&$1, $3); $$.vstride = $2.vstride; $$.width = $2.width; $$.hstride = $2.hstride; @@ -1648,32 +1621,28 @@ srcarcoperandex: } ; -srcarcoperandex_ud_typed: - controlreg - | statereg - | ipreg - | channelenablereg - ; - srcarcoperandex_typed: - flagreg + channelenablereg + | controlreg + | flagreg + | ipreg | maskreg | statereg ; indirectsrcoperand: - negate abs indirectgenreg indirectregion swizzle srctype + negate abs indirectgenreg indirectregion swizzle reg_type { $$ = brw_reg($3.file, 0, $3.subnr, $1, // negate $2, // abs - $6.type, + $6, $4.vstride, $4.width, $4.hstride, - $5.swizzle, + $5, WRITEMASK_X); $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; @@ -1691,18 +1660,18 @@ directgenreg_list: ; directsrcoperand: - negate abs directgenreg_list region swizzle srctype + negate abs directgenreg_list region swizzle reg_type { $$ = brw_reg($3.file, $3.nr, $3.subnr, $1, $2, - $6.type, + $6, $4.vstride, $4.width, $4.hstride, - $5.swizzle, + $5, WRITEMASK_X); } | srcarcoperandex @@ -1774,7 +1743,7 @@ addrreg: int subnr = (p->devinfo->gen >= 8) ? 16 : 8; if ($2 > subnr) - error(&@2, "Address sub resgister number %d" + error(&@2, "Address sub register number %d" "out of range\n", $2); $$.file = BRW_ARCHITECTURE_REGISTER_FILE; @@ -1871,7 +1840,7 @@ statereg: controlreg: CONTROLREG subregnum { - if ($2 > 4) + if ($2 > 3) error(&@2, "control sub register number %d" " out of range\n", $2); @@ -1948,7 +1917,10 @@ immval: /* Regions */ dstregion: - %empty { $$ = -1; } + %empty + { + $$ = BRW_HORIZONTAL_STRIDE_1; + } | LANGLE exp RANGLE { if ($2 != 0 && ($2 > 4 || !isPowerofTwo($2))) @@ -2031,41 +2003,36 @@ region_wh: } ; -srctype: - %empty { $$ = retype($$, BRW_REGISTER_TYPE_F); } - | TYPE_F { $$ = retype($$, BRW_REGISTER_TYPE_F); } - | TYPE_UD { $$ = retype($$, BRW_REGISTER_TYPE_UD); } - | TYPE_D { $$ = retype($$, BRW_REGISTER_TYPE_D); } - | TYPE_UW { $$ = retype($$, BRW_REGISTER_TYPE_UW); } - | TYPE_W { $$ = retype($$, BRW_REGISTER_TYPE_W); } - | TYPE_UB { $$ = retype($$, BRW_REGISTER_TYPE_UB); } - | TYPE_B { $$ = retype($$, BRW_REGISTER_TYPE_B); } - | TYPE_DF { $$ = retype($$, BRW_REGISTER_TYPE_DF); } - | TYPE_UQ { $$ = retype($$, BRW_REGISTER_TYPE_UQ); } - | TYPE_Q { $$ = retype($$, BRW_REGISTER_TYPE_Q); } - | TYPE_HF { $$ = retype($$, BRW_REGISTER_TYPE_HF); } - | TYPE_NF { $$ = retype($$, BRW_REGISTER_TYPE_NF); } - ; - -srcimmtype: - srctype { $$ = $1; } - | TYPE_V { $$ = retype($$, BRW_REGISTER_TYPE_V); } - | TYPE_VF { $$ = retype($$, BRW_REGISTER_TYPE_VF); } - | TYPE_UV { $$ = retype($$, BRW_REGISTER_TYPE_UV); } +reg_type: + TYPE_F { $$ = BRW_REGISTER_TYPE_F; } + | TYPE_UD { $$ = BRW_REGISTER_TYPE_UD; } + | TYPE_D { $$ = BRW_REGISTER_TYPE_D; } + | TYPE_UW { $$ = BRW_REGISTER_TYPE_UW; } + | TYPE_W { $$ = BRW_REGISTER_TYPE_W; } + | TYPE_UB { $$ = BRW_REGISTER_TYPE_UB; } + | TYPE_B { $$ = BRW_REGISTER_TYPE_B; } + | TYPE_DF { $$ = BRW_REGISTER_TYPE_DF; } + | TYPE_UQ { $$ = BRW_REGISTER_TYPE_UQ; } + | TYPE_Q { $$ = BRW_REGISTER_TYPE_Q; } + | TYPE_HF { $$ = BRW_REGISTER_TYPE_HF; } + | TYPE_NF { $$ = BRW_REGISTER_TYPE_NF; } ; -dsttype: - srctype { $$ = $1; } +imm_type: + reg_type { $$ = $1; } + | TYPE_V { $$ = BRW_REGISTER_TYPE_V; } + | TYPE_VF { $$ = BRW_REGISTER_TYPE_VF; } + | TYPE_UV { $$ = BRW_REGISTER_TYPE_UV; } ; writemask: %empty { - $$= brw_set_writemask($$, WRITEMASK_XYZW); + $$ = WRITEMASK_XYZW; } | DOT writemask_x writemask_y writemask_z writemask_w { - $$ = brw_set_writemask($$, $2 | $3 | $4 | $5); + $$ = $2 | $3 | $4 | $5; } ; @@ -2092,15 +2059,15 @@ writemask_w: swizzle: %empty { - $$.swizzle = BRW_SWIZZLE_NOOP; + $$ = BRW_SWIZZLE_NOOP; } | DOT chansel { - $$.swizzle = BRW_SWIZZLE4($2, $2, $2, $2); + $$ = BRW_SWIZZLE4($2, $2, $2, $2); } | DOT chansel chansel chansel chansel { - $$.swizzle = BRW_SWIZZLE4($2, $3, $4, $5); + $$ = BRW_SWIZZLE4($2, $3, $4, $5); } ;