X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fintel%2Fvulkan%2Fanv_blorp.c;h=af7f7cb9416a53cfc6553ccd97c1b24bfd9d867b;hb=aff078eb5a79dc53330ee8edfc755a995a041c74;hp=a9e664c3310aeb8d1345ec4400e5d46050333fe2;hpb=d7fe9af6202413aa4e6f0f53d89577ed8ea80027;p=mesa.git diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c index a9e664c3310..af7f7cb9416 100644 --- a/src/intel/vulkan/anv_blorp.c +++ b/src/intel/vulkan/anv_blorp.c @@ -51,7 +51,7 @@ lookup_blorp_shader(struct blorp_batch *batch, } static bool -upload_blorp_shader(struct blorp_batch *batch, +upload_blorp_shader(struct blorp_batch *batch, uint32_t stage, const void *key, uint32_t key_size, const void *kernel, uint32_t kernel_size, const struct brw_stage_prog_data *prog_data, @@ -70,9 +70,8 @@ upload_blorp_shader(struct blorp_batch *batch, }; struct anv_shader_bin *bin = - anv_pipeline_cache_upload_kernel(&device->default_pipeline_cache, + anv_pipeline_cache_upload_kernel(&device->default_pipeline_cache, stage, key, key_size, kernel, kernel_size, - NULL, 0, prog_data, prog_data_size, NULL, 0, NULL, &bind_map); @@ -1580,7 +1579,7 @@ anv_image_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer, * cache before rendering to it. */ cmd_buffer->state.pending_pipe_bits |= - ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT; + ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT; blorp_clear_depth_stencil(&batch, &depth, &stencil, level, base_layer, layer_count, @@ -1597,7 +1596,7 @@ anv_image_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer, * cache before someone starts trying to do stencil on it. */ cmd_buffer->state.pending_pipe_bits |= - ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT; + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT; struct blorp_surf stencil_shadow; if ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && @@ -1628,8 +1627,8 @@ anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer, { assert(aspect == VK_IMAGE_ASPECT_DEPTH_BIT); assert(base_layer + layer_count <= anv_image_aux_layers(image, aspect, level)); - assert(anv_image_aspect_to_plane(image->aspects, - VK_IMAGE_ASPECT_DEPTH_BIT) == 0); + uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect); + assert(plane == 0); struct blorp_batch batch; blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0); @@ -1638,7 +1637,7 @@ anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer, get_blorp_surf_for_anv_image(cmd_buffer->device, image, VK_IMAGE_ASPECT_DEPTH_BIT, 0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX, - ISL_AUX_USAGE_HIZ, &surf); + image->planes[plane].aux_usage, &surf); surf.clear_color.f32[0] = ANV_HZ_FC_VAL; blorp_hiz_op(&batch, &surf, level, base_layer, layer_count, hiz_op); @@ -1662,21 +1661,25 @@ anv_image_hiz_clear(struct anv_cmd_buffer *cmd_buffer, struct blorp_surf depth = {}; if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) { + uint32_t plane = anv_image_aspect_to_plane(image->aspects, + VK_IMAGE_ASPECT_DEPTH_BIT); assert(base_layer + layer_count <= anv_image_aux_layers(image, VK_IMAGE_ASPECT_DEPTH_BIT, level)); get_blorp_surf_for_anv_image(cmd_buffer->device, image, VK_IMAGE_ASPECT_DEPTH_BIT, 0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX, - ISL_AUX_USAGE_HIZ, &depth); + image->planes[plane].aux_usage, &depth); depth.clear_color.f32[0] = ANV_HZ_FC_VAL; } struct blorp_surf stencil = {}; if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) { + uint32_t plane = anv_image_aspect_to_plane(image->aspects, + VK_IMAGE_ASPECT_STENCIL_BIT); get_blorp_surf_for_anv_image(cmd_buffer->device, image, VK_IMAGE_ASPECT_STENCIL_BIT, 0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX, - ISL_AUX_USAGE_NONE, &stencil); + image->planes[plane].aux_usage, &stencil); } /* From the Sky Lake PRM Volume 7, "Depth Buffer Clear": @@ -1732,7 +1735,7 @@ anv_image_hiz_clear(struct anv_cmd_buffer *cmd_buffer, void anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer, const struct anv_image *image, - enum isl_format format, + enum isl_format format, struct isl_swizzle swizzle, VkImageAspectFlagBits aspect, uint32_t base_layer, uint32_t layer_count, enum isl_aux_op mcs_op, union isl_color_value *clear_value, @@ -1778,11 +1781,11 @@ anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer, * that it is completed before any additional drawing occurs. */ cmd_buffer->state.pending_pipe_bits |= - ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT; + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT; switch (mcs_op) { case ISL_AUX_OP_FAST_CLEAR: - blorp_fast_clear(&batch, &surf, format, + blorp_fast_clear(&batch, &surf, format, swizzle, 0, base_layer, layer_count, 0, 0, image->extent.width, image->extent.height); break; @@ -1797,7 +1800,7 @@ anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer, } cmd_buffer->state.pending_pipe_bits |= - ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT; + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT; blorp_batch_finish(&batch); } @@ -1805,7 +1808,7 @@ anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer, void anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer, const struct anv_image *image, - enum isl_format format, + enum isl_format format, struct isl_swizzle swizzle, VkImageAspectFlagBits aspect, uint32_t level, uint32_t base_layer, uint32_t layer_count, enum isl_aux_op ccs_op, union isl_color_value *clear_value, @@ -1859,11 +1862,11 @@ anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer, * that it is completed before any additional drawing occurs. */ cmd_buffer->state.pending_pipe_bits |= - ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT; + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT; switch (ccs_op) { case ISL_AUX_OP_FAST_CLEAR: - blorp_fast_clear(&batch, &surf, format, + blorp_fast_clear(&batch, &surf, format, swizzle, level, base_layer, layer_count, 0, 0, level_width, level_height); break; @@ -1883,7 +1886,7 @@ anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer, } cmd_buffer->state.pending_pipe_bits |= - ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT; + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT; blorp_batch_finish(&batch); }