X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fintel%2Fvulkan%2Fanv_pipeline.c;h=97bc840e6177af05b91833dfc5153b64179a9e8c;hb=6b31229592df76eefc1aa41d5b936ad2bb6b5598;hp=fdec3ce6227b5aaba182a5a81bf9d97383a257fa;hpb=e50d4807a35e6798371e12f745f75419795d3564;p=mesa.git diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index fdec3ce6227..97bc840e617 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -30,7 +30,7 @@ #include "util/mesa-sha1.h" #include "common/gen_l3_config.h" #include "anv_private.h" -#include "brw_nir.h" +#include "compiler/brw_nir.h" #include "anv_nir.h" #include "spirv/nir_spirv.h" @@ -87,15 +87,14 @@ void anv_DestroyShaderModule( * we can't do that yet because we don't have the ability to copy nir. */ static nir_shader * -anv_shader_compile_to_nir(struct anv_device *device, +anv_shader_compile_to_nir(struct anv_pipeline *pipeline, + void *mem_ctx, struct anv_shader_module *module, const char *entrypoint_name, gl_shader_stage stage, const VkSpecializationInfo *spec_info) { - if (strcmp(entrypoint_name, "main") != 0) { - anv_finishme("Multiple shaders per module not really supported"); - } + const struct anv_device *device = pipeline->device; const struct brw_compiler *compiler = device->instance->physicalDevice.compiler; @@ -126,6 +125,12 @@ anv_shader_compile_to_nir(struct anv_device *device, const struct nir_spirv_supported_extensions supported_ext = { .float64 = device->instance->physicalDevice.info.gen >= 8, + .int64 = device->instance->physicalDevice.info.gen >= 8, + .tessellation = true, + .draw_parameters = true, + .image_write_without_format = true, + .multiview = true, + .variable_pointers = true, }; nir_function *entry_point = @@ -135,12 +140,10 @@ anv_shader_compile_to_nir(struct anv_device *device, nir_shader *nir = entry_point->shader; assert(nir->stage == stage); nir_validate_shader(nir); + ralloc_steal(mem_ctx, nir); free(spec_entries); - if (stage == MESA_SHADER_FRAGMENT) - NIR_PASS_V(nir, nir_lower_wpos_center); - /* We have to lower away local constant initializers right before we * inline functions. That way they get properly initialized at the top * of the function and not at the top of its caller. @@ -160,6 +163,9 @@ anv_shader_compile_to_nir(struct anv_device *device, NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_shader_in | nir_var_shader_out | nir_var_system_value); + if (stage == MESA_SHADER_FRAGMENT) + NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable); + /* Now that we've deleted all but the main function, we can go ahead and * lower the rest of the constant initializers. */ @@ -170,7 +176,7 @@ anv_shader_compile_to_nir(struct anv_device *device, NIR_PASS_V(nir, nir_lower_system_values); /* Vulkan uses the separate-shader linking model */ - nir->info->separate_shader = true; + nir->info.separate_shader = true; nir = brw_preprocess_nir(compiler, nir); @@ -179,8 +185,6 @@ anv_shader_compile_to_nir(struct anv_device *device, if (stage == MESA_SHADER_FRAGMENT) NIR_PASS_V(nir, anv_nir_lower_input_attachments); - nir_shader_gather_info(nir, entry_point->impl); - return nir; } @@ -225,6 +229,25 @@ static void populate_sampler_prog_key(const struct gen_device_info *devinfo, struct brw_sampler_prog_key_data *key) { + /* Almost all multisampled textures are compressed. The only time when we + * don't compress a multisampled texture is for 16x MSAA with a surface + * width greater than 8k which is a bit of an edge case. Since the sampler + * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe + * to tell the compiler to always assume compression. + */ + key->compressed_multisample_layout_mask = ~0; + + /* SkyLake added support for 16x MSAA. With this came a new message for + * reading from a 16x MSAA surface with compression. The new message was + * needed because now the MCS data is 64 bits instead of 32 or lower as is + * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which + * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x + * so we can just use it unconditionally. This may not be quite as + * efficient but it saves us from recompiling. + */ + if (devinfo->gen >= 9) + key->msaa_16 = ~0; + /* XXX: Handle texture swizzle on HSW- */ for (int i = 0; i < MAX_SAMPLERS; i++) { /* Assume color sampler, no swizzling. (Works for BDW+) */ @@ -260,7 +283,6 @@ populate_wm_prog_key(const struct anv_pipeline *pipeline, struct brw_wm_prog_key *key) { const struct gen_device_info *devinfo = &pipeline->device->info; - ANV_FROM_HANDLE(anv_render_pass, render_pass, info->renderPass); memset(key, 0, sizeof(*key)); @@ -269,7 +291,7 @@ populate_wm_prog_key(const struct anv_pipeline *pipeline, /* TODO: we could set this to 0 based on the information in nir_shader, but * this function is called before spirv_to_nir. */ const struct brw_vue_map *vue_map = - anv_pipeline_get_fs_input_map(pipeline); + &anv_pipeline_get_last_vue_prog_data(pipeline)->vue_map; key->input_slots_valid = vue_map->slots_valid; /* Vulkan doesn't specify a default */ @@ -278,21 +300,25 @@ populate_wm_prog_key(const struct anv_pipeline *pipeline, /* XXX Vulkan doesn't appear to specify */ key->clamp_fragment_color = false; - key->nr_color_regions = - render_pass->subpasses[info->subpass].color_count; + key->nr_color_regions = pipeline->subpass->color_count; key->replicate_alpha = key->nr_color_regions > 1 && info->pMultisampleState && info->pMultisampleState->alphaToCoverageEnable; - if (info->pMultisampleState && info->pMultisampleState->rasterizationSamples > 1) { + if (info->pMultisampleState) { /* We should probably pull this out of the shader, but it's fairly * harmless to compute it and then let dead-code take care of it. */ - key->persample_interp = - (info->pMultisampleState->minSampleShading * - info->pMultisampleState->rasterizationSamples) > 1; - key->multisample_fbo = true; + if (info->pMultisampleState->rasterizationSamples > 1) { + key->persample_interp = + (info->pMultisampleState->minSampleShading * + info->pMultisampleState->rasterizationSamples) > 1; + key->multisample_fbo = true; + } + + key->frag_coord_adds_sample_pos = + info->pMultisampleState->sampleShadingEnable; } } @@ -305,8 +331,41 @@ populate_cs_prog_key(const struct gen_device_info *devinfo, populate_sampler_prog_key(devinfo, &key->tex); } +static void +anv_pipeline_hash_shader(struct anv_pipeline *pipeline, + struct anv_shader_module *module, + const char *entrypoint, + gl_shader_stage stage, + const VkSpecializationInfo *spec_info, + const void *key, size_t key_size, + unsigned char *sha1_out) +{ + struct mesa_sha1 ctx; + + _mesa_sha1_init(&ctx); + if (stage != MESA_SHADER_COMPUTE) { + _mesa_sha1_update(&ctx, &pipeline->subpass->view_mask, + sizeof(pipeline->subpass->view_mask)); + } + if (pipeline->layout) { + _mesa_sha1_update(&ctx, pipeline->layout->sha1, + sizeof(pipeline->layout->sha1)); + } + _mesa_sha1_update(&ctx, module->sha1, sizeof(module->sha1)); + _mesa_sha1_update(&ctx, entrypoint, strlen(entrypoint)); + _mesa_sha1_update(&ctx, &stage, sizeof(stage)); + if (spec_info) { + _mesa_sha1_update(&ctx, spec_info->pMapEntries, + spec_info->mapEntryCount * sizeof(*spec_info->pMapEntries)); + _mesa_sha1_update(&ctx, spec_info->pData, spec_info->dataSize); + } + _mesa_sha1_update(&ctx, key, key_size); + _mesa_sha1_final(&ctx, sha1_out); +} + static nir_shader * anv_pipeline_compile(struct anv_pipeline *pipeline, + void *mem_ctx, struct anv_shader_module *module, const char *entrypoint, gl_shader_stage stage, @@ -314,14 +373,26 @@ anv_pipeline_compile(struct anv_pipeline *pipeline, struct brw_stage_prog_data *prog_data, struct anv_pipeline_bind_map *map) { - nir_shader *nir = anv_shader_compile_to_nir(pipeline->device, + nir_shader *nir = anv_shader_compile_to_nir(pipeline, mem_ctx, module, entrypoint, stage, spec_info); if (nir == NULL) return NULL; + NIR_PASS_V(nir, anv_nir_lower_ycbcr_textures, pipeline); + NIR_PASS_V(nir, anv_nir_lower_push_constants); + if (stage != MESA_SHADER_COMPUTE) + NIR_PASS_V(nir, anv_nir_lower_multiview, pipeline->subpass->view_mask); + + if (stage == MESA_SHADER_COMPUTE) { + NIR_PASS_V(nir, brw_nir_lower_cs_shared); + prog_data->total_shared = nir->num_shared; + } + + nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir)); + /* Figure out the number of parameters */ prog_data->nr_params = 0; @@ -330,28 +401,15 @@ anv_pipeline_compile(struct anv_pipeline *pipeline, * them the maximum possible number */ assert(nir->num_uniforms <= MAX_PUSH_CONSTANTS_SIZE); + nir->num_uniforms = MAX_PUSH_CONSTANTS_SIZE; prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float); } - if (pipeline->layout && pipeline->layout->stage[stage].has_dynamic_offsets) - prog_data->nr_params += MAX_DYNAMIC_BUFFERS * 2; - - if (nir->info->num_images > 0) { - prog_data->nr_params += nir->info->num_images * BRW_IMAGE_PARAM_SIZE; - pipeline->needs_data_cache = true; - } - - if (stage == MESA_SHADER_COMPUTE) - ((struct brw_cs_prog_data *)prog_data)->thread_local_id_index = - prog_data->nr_params++; /* The CS Thread ID uniform */ - - if (nir->info->num_ssbos > 0) + if (nir->info.num_ssbos > 0 || nir->info.num_images > 0) pipeline->needs_data_cache = true; if (prog_data->nr_params > 0) { - /* XXX: I think we're leaking this */ - prog_data->param = (const union gl_constant_value **) - malloc(prog_data->nr_params * sizeof(union gl_constant_value *)); + prog_data->param = ralloc_array(mem_ctx, uint32_t, prog_data->nr_params); /* We now set the param values to be offsets into a * anv_push_constant_data structure. Since the compiler doesn't @@ -362,22 +420,16 @@ anv_pipeline_compile(struct anv_pipeline *pipeline, if (nir->num_uniforms > 0) { /* Fill out the push constants section of the param array */ for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++) - prog_data->param[i] = (const union gl_constant_value *) - &null_data->client_data[i * sizeof(float)]; + prog_data->param[i] = ANV_PARAM_PUSH( + (uintptr_t)&null_data->client_data[i * sizeof(float)]); } } - /* Set up dynamic offsets */ - anv_nir_apply_dynamic_offsets(pipeline, nir, prog_data); - /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */ if (pipeline->layout) anv_nir_apply_pipeline_layout(pipeline, nir, prog_data, map); - /* nir_lower_io will only handle the push constants; we need to set this - * to the full number of possible uniforms. - */ - nir->num_uniforms = prog_data->nr_params * 4; + assert(nir->num_uniforms == prog_data->nr_params * 4); return nir; } @@ -435,7 +487,6 @@ anv_pipeline_compile_vs(struct anv_pipeline *pipeline, { const struct brw_compiler *compiler = pipeline->device->instance->physicalDevice.compiler; - struct anv_pipeline_bind_map map; struct brw_vs_prog_key key; struct anv_shader_bin *bin = NULL; unsigned char sha1[20]; @@ -443,45 +494,44 @@ anv_pipeline_compile_vs(struct anv_pipeline *pipeline, populate_vs_prog_key(&pipeline->device->info, &key); if (cache) { - anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, - pipeline->layout, spec_info); + anv_pipeline_hash_shader(pipeline, module, entrypoint, + MESA_SHADER_VERTEX, spec_info, + &key, sizeof(key), sha1); bin = anv_pipeline_cache_search(cache, sha1, 20); } if (bin == NULL) { - struct brw_vs_prog_data prog_data = { 0, }; + struct brw_vs_prog_data prog_data = {}; struct anv_pipeline_binding surface_to_descriptor[256]; struct anv_pipeline_binding sampler_to_descriptor[256]; - map = (struct anv_pipeline_bind_map) { + struct anv_pipeline_bind_map map = { .surface_to_descriptor = surface_to_descriptor, .sampler_to_descriptor = sampler_to_descriptor }; - nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint, + void *mem_ctx = ralloc_context(NULL); + + nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, + module, entrypoint, MESA_SHADER_VERTEX, spec_info, &prog_data.base.base, &map); - if (nir == NULL) + if (nir == NULL) { + ralloc_free(mem_ctx); return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY); + } anv_fill_binding_table(&prog_data.base.base, 0); - void *mem_ctx = ralloc_context(NULL); - - ralloc_steal(mem_ctx, nir); - - prog_data.inputs_read = nir->info->inputs_read; - prog_data.double_inputs_read = nir->info->double_inputs_read; - brw_compute_vue_map(&pipeline->device->info, &prog_data.base.vue_map, - nir->info->outputs_written, - nir->info->separate_shader); + nir->info.outputs_written, + nir->info.separate_shader); unsigned code_size; const unsigned *shader_code = brw_compile_vs(compiler, NULL, mem_ctx, &key, &prog_data, nir, - NULL, false, -1, &code_size, NULL); + false, -1, &code_size, NULL); if (shader_code == NULL) { ralloc_free(mem_ctx); return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY); @@ -535,6 +585,10 @@ merge_tess_info(struct shader_info *tes_info, tcs_info->tess.spacing == tes_info->tess.spacing); tes_info->tess.spacing |= tcs_info->tess.spacing; + assert(tcs_info->tess.primitive_mode == 0 || + tes_info->tess.primitive_mode == 0 || + tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode); + tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode; tes_info->tess.ccw |= tcs_info->tess.ccw; tes_info->tess.point_mode |= tcs_info->tess.point_mode; } @@ -553,10 +607,8 @@ anv_pipeline_compile_tcs_tes(struct anv_pipeline *pipeline, const struct gen_device_info *devinfo = &pipeline->device->info; const struct brw_compiler *compiler = pipeline->device->instance->physicalDevice.compiler; - struct anv_pipeline_bind_map tcs_map; - struct anv_pipeline_bind_map tes_map; - struct brw_tcs_prog_key tcs_key = { 0, }; - struct brw_tes_prog_key tes_key = { 0, }; + struct brw_tcs_prog_key tcs_key = {}; + struct brw_tes_prog_key tes_key = {}; struct anv_shader_bin *tcs_bin = NULL; struct anv_shader_bin *tes_bin = NULL; unsigned char tcs_sha1[40]; @@ -567,10 +619,12 @@ anv_pipeline_compile_tcs_tes(struct anv_pipeline *pipeline, tcs_key.input_vertices = info->pTessellationState->patchControlPoints; if (cache) { - anv_hash_shader(tcs_sha1, &tcs_key, sizeof(tcs_key), tcs_module, - tcs_entrypoint, pipeline->layout, tcs_spec_info); - anv_hash_shader(tes_sha1, &tes_key, sizeof(tes_key), tes_module, - tes_entrypoint, pipeline->layout, tes_spec_info); + anv_pipeline_hash_shader(pipeline, tcs_module, tcs_entrypoint, + MESA_SHADER_TESS_CTRL, tcs_spec_info, + &tcs_key, sizeof(tcs_key), tcs_sha1); + anv_pipeline_hash_shader(pipeline, tes_module, tes_entrypoint, + MESA_SHADER_TESS_EVAL, tes_spec_info, + &tes_key, sizeof(tes_key), tes_sha1); memcpy(&tcs_sha1[20], tes_sha1, 20); memcpy(&tes_sha1[20], tcs_sha1, 20); tcs_bin = anv_pipeline_cache_search(cache, tcs_sha1, sizeof(tcs_sha1)); @@ -578,58 +632,57 @@ anv_pipeline_compile_tcs_tes(struct anv_pipeline *pipeline, } if (tcs_bin == NULL || tes_bin == NULL) { - struct brw_tcs_prog_data tcs_prog_data = { 0, }; - struct brw_tes_prog_data tes_prog_data = { 0, }; + struct brw_tcs_prog_data tcs_prog_data = {}; + struct brw_tes_prog_data tes_prog_data = {}; struct anv_pipeline_binding tcs_surface_to_descriptor[256]; struct anv_pipeline_binding tcs_sampler_to_descriptor[256]; struct anv_pipeline_binding tes_surface_to_descriptor[256]; struct anv_pipeline_binding tes_sampler_to_descriptor[256]; - tcs_map = (struct anv_pipeline_bind_map) { + struct anv_pipeline_bind_map tcs_map = { .surface_to_descriptor = tcs_surface_to_descriptor, .sampler_to_descriptor = tcs_sampler_to_descriptor }; - tes_map = (struct anv_pipeline_bind_map) { + struct anv_pipeline_bind_map tes_map = { .surface_to_descriptor = tes_surface_to_descriptor, .sampler_to_descriptor = tes_sampler_to_descriptor }; + void *mem_ctx = ralloc_context(NULL); + nir_shader *tcs_nir = - anv_pipeline_compile(pipeline, tcs_module, tcs_entrypoint, + anv_pipeline_compile(pipeline, mem_ctx, tcs_module, tcs_entrypoint, MESA_SHADER_TESS_CTRL, tcs_spec_info, &tcs_prog_data.base.base, &tcs_map); nir_shader *tes_nir = - anv_pipeline_compile(pipeline, tes_module, tes_entrypoint, + anv_pipeline_compile(pipeline, mem_ctx, tes_module, tes_entrypoint, MESA_SHADER_TESS_EVAL, tes_spec_info, &tes_prog_data.base.base, &tes_map); - if (tcs_nir == NULL || tes_nir == NULL) + if (tcs_nir == NULL || tes_nir == NULL) { + ralloc_free(mem_ctx); return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY); + } nir_lower_tes_patch_vertices(tes_nir, - tcs_nir->info->tess.tcs_vertices_out); + tcs_nir->info.tess.tcs_vertices_out); /* Copy TCS info into the TES info */ - merge_tess_info(tes_nir->info, tcs_nir->info); + merge_tess_info(&tes_nir->info, &tcs_nir->info); anv_fill_binding_table(&tcs_prog_data.base.base, 0); anv_fill_binding_table(&tes_prog_data.base.base, 0); - void *mem_ctx = ralloc_context(NULL); - - ralloc_steal(mem_ctx, tcs_nir); - ralloc_steal(mem_ctx, tes_nir); - /* Whacking the key after cache lookup is a bit sketchy, but all of * this comes from the SPIR-V, which is part of the hash used for the * pipeline cache. So it should be safe. */ - tcs_key.tes_primitive_mode = tes_nir->info->tess.primitive_mode; - tcs_key.outputs_written = tcs_nir->info->outputs_written; - tcs_key.patch_outputs_written = tcs_nir->info->patch_outputs_written; + tcs_key.tes_primitive_mode = tes_nir->info.tess.primitive_mode; + tcs_key.outputs_written = tcs_nir->info.outputs_written; + tcs_key.patch_outputs_written = tcs_nir->info.patch_outputs_written; tcs_key.quads_workaround = devinfo->gen < 9 && - tes_nir->info->tess.primitive_mode == 7 /* GL_QUADS */ && - tes_nir->info->tess.spacing == TESS_SPACING_EQUAL; + tes_nir->info.tess.primitive_mode == 7 /* GL_QUADS */ && + tes_nir->info.tess.spacing == TESS_SPACING_EQUAL; tes_key.inputs_read = tcs_key.outputs_written; tes_key.patch_inputs_read = tcs_key.patch_outputs_written; @@ -696,7 +749,6 @@ anv_pipeline_compile_gs(struct anv_pipeline *pipeline, { const struct brw_compiler *compiler = pipeline->device->instance->physicalDevice.compiler; - struct anv_pipeline_bind_map map; struct brw_gs_prog_key key; struct anv_shader_bin *bin = NULL; unsigned char sha1[20]; @@ -704,37 +756,39 @@ anv_pipeline_compile_gs(struct anv_pipeline *pipeline, populate_gs_prog_key(&pipeline->device->info, &key); if (cache) { - anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, - pipeline->layout, spec_info); + anv_pipeline_hash_shader(pipeline, module, entrypoint, + MESA_SHADER_GEOMETRY, spec_info, + &key, sizeof(key), sha1); bin = anv_pipeline_cache_search(cache, sha1, 20); } if (bin == NULL) { - struct brw_gs_prog_data prog_data = { 0, }; + struct brw_gs_prog_data prog_data = {}; struct anv_pipeline_binding surface_to_descriptor[256]; struct anv_pipeline_binding sampler_to_descriptor[256]; - map = (struct anv_pipeline_bind_map) { + struct anv_pipeline_bind_map map = { .surface_to_descriptor = surface_to_descriptor, .sampler_to_descriptor = sampler_to_descriptor }; - nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint, + void *mem_ctx = ralloc_context(NULL); + + nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, + module, entrypoint, MESA_SHADER_GEOMETRY, spec_info, &prog_data.base.base, &map); - if (nir == NULL) + if (nir == NULL) { + ralloc_free(mem_ctx); return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY); + } anv_fill_binding_table(&prog_data.base.base, 0); - void *mem_ctx = ralloc_context(NULL); - - ralloc_steal(mem_ctx, nir); - brw_compute_vue_map(&pipeline->device->info, &prog_data.base.vue_map, - nir->info->outputs_written, - nir->info->separate_shader); + nir->info.outputs_written, + nir->info.separate_shader); unsigned code_size; const unsigned *shader_code = @@ -773,7 +827,6 @@ anv_pipeline_compile_fs(struct anv_pipeline *pipeline, { const struct brw_compiler *compiler = pipeline->device->instance->physicalDevice.compiler; - struct anv_pipeline_bind_map map; struct brw_wm_prog_key key; struct anv_shader_bin *bin = NULL; unsigned char sha1[20]; @@ -781,26 +834,32 @@ anv_pipeline_compile_fs(struct anv_pipeline *pipeline, populate_wm_prog_key(pipeline, info, &key); if (cache) { - anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, - pipeline->layout, spec_info); + anv_pipeline_hash_shader(pipeline, module, entrypoint, + MESA_SHADER_FRAGMENT, spec_info, + &key, sizeof(key), sha1); bin = anv_pipeline_cache_search(cache, sha1, 20); } if (bin == NULL) { - struct brw_wm_prog_data prog_data = { 0, }; + struct brw_wm_prog_data prog_data = {}; struct anv_pipeline_binding surface_to_descriptor[256]; struct anv_pipeline_binding sampler_to_descriptor[256]; - map = (struct anv_pipeline_bind_map) { + struct anv_pipeline_bind_map map = { .surface_to_descriptor = surface_to_descriptor + 8, .sampler_to_descriptor = sampler_to_descriptor }; - nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint, + void *mem_ctx = ralloc_context(NULL); + + nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, + module, entrypoint, MESA_SHADER_FRAGMENT, spec_info, &prog_data.base, &map); - if (nir == NULL) + if (nir == NULL) { + ralloc_free(mem_ctx); return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY); + } unsigned num_rts = 0; struct anv_pipeline_binding rt_bindings[8]; @@ -841,7 +900,7 @@ anv_pipeline_compile_fs(struct anv_pipeline *pipeline, rt_bindings[0] = (struct anv_pipeline_binding) { .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS, .binding = 0, - .index = UINT8_MAX, + .index = UINT32_MAX, }; num_rts = 1; } @@ -855,10 +914,6 @@ anv_pipeline_compile_fs(struct anv_pipeline *pipeline, anv_fill_binding_table(&prog_data.base, num_rts); - void *mem_ctx = ralloc_context(NULL); - - ralloc_steal(mem_ctx, nir); - unsigned code_size; const unsigned *shader_code = brw_compile_fs(compiler, NULL, mem_ctx, &key, &prog_data, nir, @@ -895,7 +950,6 @@ anv_pipeline_compile_cs(struct anv_pipeline *pipeline, { const struct brw_compiler *compiler = pipeline->device->instance->physicalDevice.compiler; - struct anv_pipeline_bind_map map; struct brw_cs_prog_key key; struct anv_shader_bin *bin = NULL; unsigned char sha1[20]; @@ -903,33 +957,35 @@ anv_pipeline_compile_cs(struct anv_pipeline *pipeline, populate_cs_prog_key(&pipeline->device->info, &key); if (cache) { - anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, - pipeline->layout, spec_info); + anv_pipeline_hash_shader(pipeline, module, entrypoint, + MESA_SHADER_COMPUTE, spec_info, + &key, sizeof(key), sha1); bin = anv_pipeline_cache_search(cache, sha1, 20); } if (bin == NULL) { - struct brw_cs_prog_data prog_data = { 0, }; + struct brw_cs_prog_data prog_data = {}; struct anv_pipeline_binding surface_to_descriptor[256]; struct anv_pipeline_binding sampler_to_descriptor[256]; - map = (struct anv_pipeline_bind_map) { + struct anv_pipeline_bind_map map = { .surface_to_descriptor = surface_to_descriptor, .sampler_to_descriptor = sampler_to_descriptor }; - nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint, + void *mem_ctx = ralloc_context(NULL); + + nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, + module, entrypoint, MESA_SHADER_COMPUTE, spec_info, &prog_data.base, &map); - if (nir == NULL) + if (nir == NULL) { + ralloc_free(mem_ctx); return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY); + } anv_fill_binding_table(&prog_data.base, 1); - void *mem_ctx = ralloc_context(NULL); - - ralloc_steal(mem_ctx, nir); - unsigned code_size; const unsigned *shader_code = brw_compile_cs(compiler, NULL, mem_ctx, &key, &prog_data, nir, @@ -974,8 +1030,7 @@ copy_non_dynamic_state(struct anv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo) { anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL; - ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass); - struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass]; + struct anv_subpass *subpass = pipeline->subpass; pipeline->dynamic_state = default_dynamic_state; @@ -1034,7 +1089,7 @@ copy_non_dynamic_state(struct anv_pipeline *pipeline, */ bool uses_color_att = false; for (unsigned i = 0; i < subpass->color_count; ++i) { - if (subpass->color_attachments[i] != VK_ATTACHMENT_UNUSED) { + if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) { uses_color_att = true; break; } @@ -1062,7 +1117,7 @@ copy_non_dynamic_state(struct anv_pipeline *pipeline, * against does not use a depth/stencil attachment. */ if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable && - subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) { + subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) { assert(pCreateInfo->pDepthStencilState); if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) { @@ -1100,6 +1155,7 @@ copy_non_dynamic_state(struct anv_pipeline *pipeline, static void anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info) { +#ifdef DEBUG struct anv_render_pass *renderpass = NULL; struct anv_subpass *subpass = NULL; @@ -1122,7 +1178,7 @@ anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info) assert(info->pViewportState); assert(info->pMultisampleState); - if (subpass && subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) + if (subpass && subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) assert(info->pDepthStencilState); if (subpass && subpass->color_count > 0) @@ -1139,6 +1195,7 @@ anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info) break; } } +#endif } /** @@ -1170,14 +1227,17 @@ anv_pipeline_init(struct anv_pipeline *pipeline, { VkResult result; - anv_validate { - anv_pipeline_validate_create_info(pCreateInfo); - } + anv_pipeline_validate_create_info(pCreateInfo); if (alloc == NULL) alloc = &device->alloc; pipeline->device = device; + + ANV_FROM_HANDLE(anv_render_pass, render_pass, pCreateInfo->renderPass); + assert(pCreateInfo->subpass < render_pass->subpass_count); + pipeline->subpass = &render_pass->subpasses[pCreateInfo->subpass]; + pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout); result = anv_reloc_list_init(&pipeline->batch_relocs, alloc); @@ -1188,11 +1248,15 @@ anv_pipeline_init(struct anv_pipeline *pipeline, pipeline->batch.next = pipeline->batch.start = pipeline->batch_data; pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data); pipeline->batch.relocs = &pipeline->batch_relocs; + pipeline->batch.status = VK_SUCCESS; copy_non_dynamic_state(pipeline, pCreateInfo); pipeline->depth_clamp_enable = pCreateInfo->pRasterizationState && pCreateInfo->pRasterizationState->depthClampEnable; + pipeline->sample_shading_enable = pCreateInfo->pMultisampleState && + pCreateInfo->pMultisampleState->sampleShadingEnable; + pipeline->needs_data_cache = false; /* When we free the pipeline, we detect stages based on the NULL status @@ -1202,8 +1266,8 @@ anv_pipeline_init(struct anv_pipeline *pipeline, pipeline->active_stages = 0; - const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, }; - struct anv_shader_module *modules[MESA_SHADER_STAGES] = { 0, }; + const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = {}; + struct anv_shader_module *modules[MESA_SHADER_STAGES] = {}; for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) { gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1; pStages[stage] = &pCreateInfo->pStages[i]; @@ -1261,7 +1325,7 @@ anv_pipeline_init(struct anv_pipeline *pipeline, const VkVertexInputAttributeDescription *desc = &vi_info->pVertexAttributeDescriptions[i]; - if (inputs_read & (1 << (VERT_ATTRIB_GENERIC0 + desc->location))) + if (inputs_read & (1ull << (VERT_ATTRIB_GENERIC0 + desc->location))) pipeline->vb_used |= 1 << desc->binding; }