X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fintel%2Fvulkan%2Fanv_private.h;h=7c5dc5624515c399a105f5da5bf6b0eca8dd2b97;hb=700bebb958e93f4d472c383de62ced9db8e64bec;hp=94a13d7d331d1293cb7129e498778f06f686305b;hpb=a5dc3c0f02aa523d1d3d123b62b9a187821079fe;p=mesa.git diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 94a13d7d331..38554166570 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -21,7 +21,8 @@ * IN THE SOFTWARE. */ -#pragma once +#ifndef ANV_PRIVATE_H +#define ANV_PRIVATE_H #include #include @@ -40,10 +41,13 @@ #define VG(x) #endif -#include "brw_device_info.h" -#include "brw_compiler.h" +#include "common/gen_device_info.h" +#include "blorp/blorp.h" +#include "compiler/brw_compiler.h" #include "util/macros.h" #include "util/list.h" +#include "util/u_vector.h" +#include "util/vk_alloc.h" /* Pre-declarations needed for WSI entrypoints */ struct wl_surface; @@ -52,23 +56,38 @@ typedef struct xcb_connection_t xcb_connection_t; typedef uint32_t xcb_visualid_t; typedef uint32_t xcb_window_t; -#define VK_USE_PLATFORM_XCB_KHR -#define VK_USE_PLATFORM_WAYLAND_KHR +struct anv_buffer; +struct anv_buffer_view; +struct anv_image_view; + +struct gen_l3_config; -#define VK_PROTOTYPES #include #include #include #include "anv_entrypoints.h" -#include "brw_context.h" #include "isl/isl.h" -#ifdef __cplusplus -extern "C" { -#endif +#include "common/gen_debug.h" +#include "wsi_common.h" + +/* Allowing different clear colors requires us to perform a depth resolve at + * the end of certain render passes. This is because while slow clears store + * the clear color in the HiZ buffer, fast clears (without a resolve) don't. + * See the PRMs for examples describing when additional resolves would be + * necessary. To enable fast clears without requiring extra resolves, we set + * the clear value to a globally-defined one. We could allow different values + * if the user doesn't expect coherent data during or after a render passes + * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS) + * don't seem to exist yet. In almost all Vulkan applications tested thus far, + * 1.0f seems to be the only value used. The only application that doesn't set + * this value does so through the usage of an seemingly uninitialized clear + * value. + */ +#define ANV_HZ_FC_VAL 1.0f -#define MAX_VBS 32 +#define MAX_VBS 31 #define MAX_SETS 8 #define MAX_RTS 8 #define MAX_VIEWPORTS 16 @@ -76,13 +95,18 @@ extern "C" { #define MAX_PUSH_CONSTANTS_SIZE 128 #define MAX_DYNAMIC_BUFFERS 16 #define MAX_IMAGES 8 -#define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */ +#define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */ + +#define ANV_SVGS_VB_INDEX MAX_VBS +#define ANV_DRAWID_VB_INDEX (MAX_VBS + 1) -#define anv_noreturn __attribute__((__noreturn__)) #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b))) -#define MIN(a, b) ((a) < (b) ? (a) : (b)) -#define MAX(a, b) ((a) > (b) ? (a) : (b)) +static inline uint32_t +align_down_npot_u32(uint32_t v, uint32_t a) +{ + return v - (v % a); +} static inline uint32_t align_u32(uint32_t v, uint32_t a) @@ -119,7 +143,7 @@ anv_minify(uint32_t n, uint32_t levels) if (unlikely(n == 0)) return 0; else - return MAX(n >> levels, 1); + return MAX2(n >> levels, 1); } static inline float @@ -146,26 +170,29 @@ anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask) } } +static inline union isl_color_value +vk_to_isl_color(VkClearColorValue color) +{ + return (union isl_color_value) { + .u32 = { + color.uint32[0], + color.uint32[1], + color.uint32[2], + color.uint32[3], + }, + }; +} + #define for_each_bit(b, dword) \ for (uint32_t __dword = (dword); \ (b) = __builtin_ffs(__dword) - 1, __dword; \ __dword &= ~(1 << (b))) #define typed_memcpy(dest, src, count) ({ \ - static_assert(sizeof(*src) == sizeof(*dest), ""); \ + STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \ memcpy((dest), (src), (count) * sizeof(*(src))); \ }) -#define zero(x) (memset(&(x), 0, sizeof(x))) - -/* Define no kernel as 1, since that's an illegal offset for a kernel */ -#define NO_KERNEL 1 - -struct anv_common { - VkStructureType sType; - const void* pNext; -}; - /* Whenever we generate an error, pass it through this function. Useful for * debugging, where we can break on it. Only call at error site, not when * propagating errors. Might be useful to plug in a stack trace here. @@ -176,13 +203,35 @@ VkResult __vk_errorf(VkResult error, const char *file, int line, const char *for #ifdef DEBUG #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL); #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__); +#define anv_debug(format, ...) fprintf(stderr, "debug: " format, ##__VA_ARGS__) #else #define vk_error(error) error #define vk_errorf(error, format, ...) error +#define anv_debug(format, ...) #endif +/** + * Warn on ignored extension structs. + * + * The Vulkan spec requires us to ignore unsupported or unknown structs in + * a pNext chain. In debug mode, emitting warnings for ignored structs may + * help us discover structs that we should not have ignored. + * + * + * From the Vulkan 1.0.38 spec: + * + * Any component of the implementation (the loader, any enabled layers, + * and drivers) must skip over, without processing (other than reading the + * sType and pNext members) any chained structures with sType values not + * defined by extensions supported by that component. + */ +#define anv_debug_ignored_stype(sType) \ + anv_debug("debug: %s: ignored VkStructureType %u\n", __func__, (sType)) + void __anv_finishme(const char *file, int line, const char *format, ...) anv_printflike(3, 4); +void __anv_perf_warn(const char *file, int line, const char *format, ...) + anv_printflike(3, 4); void anv_loge(const char *format, ...) anv_printflike(1, 2); void anv_loge_v(const char *format, va_list va); @@ -190,7 +239,25 @@ void anv_loge_v(const char *format, va_list va); * Print a FINISHME message, including its source location. */ #define anv_finishme(format, ...) \ - __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); + do { \ + static bool reported = false; \ + if (!reported) { \ + __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \ + reported = true; \ + } \ + } while (0) + +/** + * Print a perf warning message. Set INTEL_DEBUG=perf to see these. + */ +#define anv_perf_warn(format, ...) \ + do { \ + static bool reported = false; \ + if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \ + __anv_perf_warn(__FILE__, __LINE__, format, ##__VA_ARGS__); \ + reported = true; \ + } \ + } while (0) /* A non-fatal assert. Useful for debugging. */ #ifdef DEBUG @@ -202,31 +269,6 @@ void anv_loge_v(const char *format, va_list va); #define anv_assert(x) #endif -/** - * If a block of code is annotated with anv_validate, then the block runs only - * in debug builds. - */ -#ifdef DEBUG -#define anv_validate if (1) -#else -#define anv_validate if (0) -#endif - -void anv_abortf(const char *format, ...) anv_noreturn anv_printflike(1, 2); -void anv_abortfv(const char *format, va_list va) anv_noreturn; - -#define stub_return(v) \ - do { \ - anv_finishme("stub %s", __func__); \ - return (v); \ - } while (0) - -#define stub() \ - do { \ - anv_finishme("stub %s", __func__); \ - return; \ - } while (0) - /** * A dynamically growable, circular buffer. Elements are added at head and * removed from tail. head and tail are free-running uint32_t indices and we @@ -235,51 +277,6 @@ void anv_abortfv(const char *format, va_list va) anv_noreturn; * wraparound. */ -struct anv_vector { - uint32_t head; - uint32_t tail; - uint32_t element_size; - uint32_t size; - void *data; -}; - -int anv_vector_init(struct anv_vector *queue, uint32_t element_size, uint32_t size); -void *anv_vector_add(struct anv_vector *queue); -void *anv_vector_remove(struct anv_vector *queue); - -static inline int -anv_vector_length(struct anv_vector *queue) -{ - return (queue->head - queue->tail) / queue->element_size; -} - -static inline void * -anv_vector_head(struct anv_vector *vector) -{ - assert(vector->tail < vector->head); - return (void *)((char *)vector->data + - ((vector->head - vector->element_size) & - (vector->size - 1))); -} - -static inline void * -anv_vector_tail(struct anv_vector *vector) -{ - return (void *)((char *)vector->data + (vector->tail & (vector->size - 1))); -} - -static inline void -anv_vector_finish(struct anv_vector *queue) -{ - free(queue->data); -} - -#define anv_vector_foreach(elem, queue) \ - static_assert(__builtin_types_compatible_p(__typeof__(queue), struct anv_vector *), ""); \ - for (uint32_t __anv_vector_offset = (queue)->tail; \ - elem = (queue)->data + (__anv_vector_offset & ((queue)->size - 1)), __anv_vector_offset < (queue)->head; \ - __anv_vector_offset += (queue)->element_size) - struct anv_bo { uint32_t gem_handle; @@ -305,6 +302,17 @@ struct anv_bo { bool is_winsys_bo; }; +static inline void +anv_bo_init(struct anv_bo *bo, uint32_t gem_handle, uint64_t size) +{ + bo->gem_handle = gem_handle; + bo->index = 0; + bo->offset = -1; + bo->size = size; + bo->map = NULL; + bo->is_winsys_bo = false; +} + /* Represents a lock-free linked list of "free" things. This is used by * both the block pool and the state pools. Unfortunately, in order to * solve the ABA problem, we can't use a single uint32_t head. @@ -358,7 +366,7 @@ struct anv_block_pool { * Array of mmaps and gem handles owned by the block pool, reclaimed when * the block pool is destroyed. */ - struct anv_vector mmap_cleanups; + struct u_vector mmap_cleanups; uint32_t block_size; @@ -370,7 +378,7 @@ struct anv_block_pool { }; /* Block pools are backed by a fixed-size 2GB memfd */ -#define BLOCK_POOL_MEMFD_SIZE (1ull << 32) +#define BLOCK_POOL_MEMFD_SIZE (1ul << 31) /* The center of the block pool is also the middle of the memfd. This may * change in the future if we decide differently for some reason. @@ -396,9 +404,9 @@ struct anv_fixed_size_state_pool { }; #define ANV_MIN_STATE_SIZE_LOG2 6 -#define ANV_MAX_STATE_SIZE_LOG2 10 +#define ANV_MAX_STATE_SIZE_LOG2 20 -#define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2) +#define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1) struct anv_state_pool { struct anv_block_pool *block_pool; @@ -430,21 +438,28 @@ anv_clflush_range(void *start, size_t size) void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK); void *end = start + size; - __builtin_ia32_mfence(); while (p < end) { __builtin_ia32_clflush(p); p += CACHELINE_SIZE; } } -static void inline -anv_state_clflush(struct anv_state state) +static inline void +anv_flush_range(void *start, size_t size) { - anv_clflush_range(state.map, state.alloc_size); + __builtin_ia32_mfence(); + anv_clflush_range(start, size); +} + +static inline void +anv_invalidate_range(void *start, size_t size) +{ + anv_clflush_range(start, size); + __builtin_ia32_mfence(); } -void anv_block_pool_init(struct anv_block_pool *pool, - struct anv_device *device, uint32_t block_size); +VkResult anv_block_pool_init(struct anv_block_pool *pool, + struct anv_device *device, uint32_t block_size); void anv_block_pool_finish(struct anv_block_pool *pool); int32_t anv_block_pool_alloc(struct anv_block_pool *pool); int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool); @@ -477,80 +492,46 @@ VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo, uint32_t size); void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo); +struct anv_scratch_bo { + bool exists; + struct anv_bo bo; +}; -void *anv_resolve_entrypoint(uint32_t index); - -extern struct anv_dispatch_table dtable; - -#define ANV_CALL(func) ({ \ - if (dtable.func == NULL) { \ - size_t idx = offsetof(struct anv_dispatch_table, func) / sizeof(void *); \ - dtable.entrypoints[idx] = anv_resolve_entrypoint(idx); \ - } \ - dtable.func; \ -}) - -static inline void * -anv_alloc(const VkAllocationCallbacks *alloc, - size_t size, size_t align, - VkSystemAllocationScope scope) -{ - return alloc->pfnAllocation(alloc->pUserData, size, align, scope); -} - -static inline void * -anv_realloc(const VkAllocationCallbacks *alloc, - void *ptr, size_t size, size_t align, - VkSystemAllocationScope scope) -{ - return alloc->pfnReallocation(alloc->pUserData, ptr, size, align, scope); -} - -static inline void -anv_free(const VkAllocationCallbacks *alloc, void *data) -{ - alloc->pfnFree(alloc->pUserData, data); -} - -static inline void * -anv_alloc2(const VkAllocationCallbacks *parent_alloc, - const VkAllocationCallbacks *alloc, - size_t size, size_t align, - VkSystemAllocationScope scope) -{ - if (alloc) - return anv_alloc(alloc, size, align, scope); - else - return anv_alloc(parent_alloc, size, align, scope); -} +struct anv_scratch_pool { + /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */ + struct anv_scratch_bo bos[16][MESA_SHADER_STAGES]; +}; -static inline void -anv_free2(const VkAllocationCallbacks *parent_alloc, - const VkAllocationCallbacks *alloc, - void *data) -{ - if (alloc) - anv_free(alloc, data); - else - anv_free(parent_alloc, data); -} +void anv_scratch_pool_init(struct anv_device *device, + struct anv_scratch_pool *pool); +void anv_scratch_pool_finish(struct anv_device *device, + struct anv_scratch_pool *pool); +struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device, + struct anv_scratch_pool *pool, + gl_shader_stage stage, + unsigned per_thread_scratch); struct anv_physical_device { VK_LOADER_DATA _loader_data; struct anv_instance * instance; uint32_t chipset_id; - const char * path; + char path[20]; const char * name; - const struct brw_device_info * info; + struct gen_device_info info; uint64_t aperture_size; struct brw_compiler * compiler; struct isl_device isl_dev; -}; + int cmd_parser_version; + + uint32_t eu_total; + uint32_t subslice_total; -struct anv_wsi_interaface; + uint8_t uuid[VK_UUID_SIZE]; -#define VK_ICD_WSI_PLATFORM_MAX 5 + struct wsi_device wsi_device; + int local_fd; +}; struct anv_instance { VK_LOADER_DATA _loader_data; @@ -560,70 +541,10 @@ struct anv_instance { uint32_t apiVersion; int physicalDeviceCount; struct anv_physical_device physicalDevice; - - struct anv_wsi_interface * wsi[VK_ICD_WSI_PLATFORM_MAX]; }; -VkResult anv_init_wsi(struct anv_instance *instance); -void anv_finish_wsi(struct anv_instance *instance); - -struct anv_meta_state { - VkAllocationCallbacks alloc; - - /** - * Use array element `i` for images with `2^i` samples. - */ - struct { - /** - * Pipeline N is used to clear color attachment N of the current - * subpass. - * - * HACK: We use one pipeline per color attachment to work around the - * compiler's inability to dynamically set the render target index of - * the render target write message. - */ - struct anv_pipeline *color_pipelines[MAX_RTS]; - - struct anv_pipeline *depth_only_pipeline; - struct anv_pipeline *stencil_only_pipeline; - struct anv_pipeline *depthstencil_pipeline; - } clear[1 + MAX_SAMPLES_LOG2]; - - struct { - VkRenderPass render_pass; - - /** Pipeline that blits from a 1D image. */ - VkPipeline pipeline_1d_src; - - /** Pipeline that blits from a 2D image. */ - VkPipeline pipeline_2d_src; - - /** Pipeline that blits from a 3D image. */ - VkPipeline pipeline_3d_src; - - VkPipelineLayout pipeline_layout; - VkDescriptorSetLayout ds_layout; - } blit; - - struct { - VkRenderPass render_pass; - - /** Pipeline that copies from a 2D image. */ - VkPipeline pipeline_2d_src; - - VkPipelineLayout pipeline_layout; - VkDescriptorSetLayout ds_layout; - } blit2d; - - struct { - /** Pipeline [i] resolves an image with 2^(i+1) samples. */ - VkPipeline pipelines[MAX_SAMPLES_LOG2]; - - VkRenderPass pass; - VkPipelineLayout pipeline_layout; - VkDescriptorSetLayout ds_layout; - } resolve; -}; +VkResult anv_init_wsi(struct anv_physical_device *physical_device); +void anv_finish_wsi(struct anv_physical_device *physical_device); struct anv_queue { VK_LOADER_DATA _loader_data; @@ -635,31 +556,28 @@ struct anv_queue { struct anv_pipeline_cache { struct anv_device * device; - struct anv_state_stream program_stream; pthread_mutex_t mutex; - uint32_t total_size; - uint32_t table_size; - uint32_t kernel_count; - uint32_t * hash_table; + struct hash_table * cache; }; struct anv_pipeline_bind_map; void anv_pipeline_cache_init(struct anv_pipeline_cache *cache, - struct anv_device *device); + struct anv_device *device, + bool cache_enabled); void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache); -uint32_t anv_pipeline_cache_search(struct anv_pipeline_cache *cache, - const unsigned char *sha1, - const struct brw_stage_prog_data **prog_data, - struct anv_pipeline_bind_map *map); -uint32_t anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache, - const unsigned char *sha1, - const void *kernel, - size_t kernel_size, - const struct brw_stage_prog_data **prog_data, - size_t prog_data_size, - struct anv_pipeline_bind_map *map); + +struct anv_shader_bin * +anv_pipeline_cache_search(struct anv_pipeline_cache *cache, + const void *key, uint32_t key_size); +struct anv_shader_bin * +anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache, + const void *key_data, uint32_t key_size, + const void *kernel_data, uint32_t kernel_size, + const struct brw_stage_prog_data *prog_data, + uint32_t prog_data_size, + const struct anv_pipeline_bind_map *bind_map); struct anv_device { VK_LOADER_DATA _loader_data; @@ -668,11 +586,12 @@ struct anv_device { struct anv_instance * instance; uint32_t chipset_id; - struct brw_device_info info; + struct gen_device_info info; struct isl_device isl_dev; int context_id; int fd; bool can_chain_batches; + bool robust_buffer_access; struct anv_bo_pool batch_bo_pool; @@ -680,28 +599,43 @@ struct anv_device { struct anv_state_pool dynamic_state_pool; struct anv_block_pool instruction_block_pool; - struct anv_pipeline_cache default_pipeline_cache; + struct anv_state_pool instruction_state_pool; struct anv_block_pool surface_state_block_pool; struct anv_state_pool surface_state_pool; struct anv_bo workaround_bo; - struct anv_meta_state meta_state; + struct anv_pipeline_cache blorp_shader_cache; + struct blorp_context blorp; struct anv_state border_colors; struct anv_queue queue; - struct anv_block_pool scratch_block_pool; + struct anv_scratch_pool scratch_pool; uint32_t default_mocs; pthread_mutex_t mutex; + pthread_cond_t queue_submit; }; -void anv_device_get_cache_uuid(void *uuid); +static void inline +anv_state_flush(struct anv_device *device, struct anv_state state) +{ + if (device->info.has_llc) + return; + + anv_flush_range(state.map, state.alloc_size); +} + +void anv_device_init_blorp(struct anv_device *device); +void anv_device_finish_blorp(struct anv_device *device); +VkResult anv_device_execbuf(struct anv_device *device, + struct drm_i915_gem_execbuffer2 *execbuf, + struct anv_bo **execbuf_bos); void* anv_gem_mmap(struct anv_device *device, uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags); @@ -753,9 +687,6 @@ struct anv_batch_bo { /* Bytes actually consumed in this batch BO */ size_t length; - /* Last seen surface state block pool bo offset */ - uint32_t last_ss_pool_bo_offset; - struct anv_reloc_list relocs; }; @@ -787,12 +718,9 @@ struct anv_address { uint32_t offset; }; -#define __gen_address_type struct anv_address -#define __gen_user_data struct anv_batch - static inline uint64_t -__gen_combine_address(struct anv_batch *batch, void *location, - const struct anv_address address, uint32_t delta) +_anv_combine_address(struct anv_batch *batch, void *location, + const struct anv_address address, uint32_t delta) { if (address.bo == NULL) { return address.offset + delta; @@ -803,6 +731,10 @@ __gen_combine_address(struct anv_batch *batch, void *location, } } +#define __gen_address_type struct anv_address +#define __gen_user_data struct anv_batch +#define __gen_combine_address _anv_combine_address + /* Wrapper macros needed to work around preprocessor argument issues. In * particular, arguments don't get pre-evaluated if they are concatenated. * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the @@ -813,15 +745,14 @@ __gen_combine_address(struct anv_batch *batch, void *location, #define __anv_cmd_length_bias(cmd) cmd ## _length_bias #define __anv_cmd_header(cmd) cmd ## _header #define __anv_cmd_pack(cmd) cmd ## _pack +#define __anv_reg_num(reg) reg ## _num -#define anv_batch_emit(batch, cmd, ...) do { \ - void *__dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \ - struct cmd __template = { \ - __anv_cmd_header(cmd), \ +#define anv_pack_struct(dst, struc, ...) do { \ + struct struc __template = { \ __VA_ARGS__ \ }; \ - __anv_cmd_pack(cmd)(batch, __dst, &__template); \ - VG(VALGRIND_CHECK_MEM_IS_DEFINED(__dst, __anv_cmd_length(cmd) * 4)); \ + __anv_cmd_pack(struc)(NULL, dst, &__template); \ + VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \ } while (0) #define anv_batch_emitn(batch, n, cmd, ...) ({ \ @@ -839,26 +770,21 @@ __gen_combine_address(struct anv_batch *batch, void *location, do { \ uint32_t *dw; \ \ - static_assert(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1), "mismatch merge"); \ + STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \ dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \ for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \ dw[i] = (dwords0)[i] | (dwords1)[i]; \ VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\ } while (0) -#define anv_state_pool_emit(pool, cmd, align, ...) ({ \ - const uint32_t __size = __anv_cmd_length(cmd) * 4; \ - struct anv_state __state = \ - anv_state_pool_alloc((pool), __size, align); \ - struct cmd __template = { \ - __VA_ARGS__ \ - }; \ - __anv_cmd_pack(cmd)(NULL, __state.map, &__template); \ - VG(VALGRIND_CHECK_MEM_IS_DEFINED(__state.map, __anv_cmd_length(cmd) * 4)); \ - if (!(pool)->block_pool->device->info.has_llc) \ - anv_state_clflush(__state); \ - __state; \ - }) +#define anv_batch_emit(batch, cmd, name) \ + for (struct cmd name = { __anv_cmd_header(cmd) }, \ + *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \ + __builtin_expect(_dst != NULL, 1); \ + ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \ + VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \ + _dst = NULL; \ + })) #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \ .GraphicsDataTypeGFDT = 0, \ @@ -909,6 +835,11 @@ struct anv_vue_header { }; struct anv_descriptor_set_binding_layout { +#ifndef NDEBUG + /* The type of the descriptors in this binding */ + VkDescriptorType type; +#endif + /* Number of array elements in this binding */ uint16_t array_size; @@ -963,6 +894,11 @@ struct anv_descriptor { struct { struct anv_image_view *image_view; struct anv_sampler *sampler; + + /* Used to determine whether or not we need the surface state to have + * the auxiliary buffer enabled. + */ + enum isl_aux_usage aux_usage; }; struct anv_buffer_view *buffer_view; @@ -977,6 +913,29 @@ struct anv_descriptor_set { struct anv_descriptor descriptors[0]; }; +struct anv_buffer_view { + enum isl_format format; /**< VkBufferViewCreateInfo::format */ + struct anv_bo *bo; + uint32_t offset; /**< Offset into bo. */ + uint64_t range; /**< VkBufferViewCreateInfo::range */ + + struct anv_state surface_state; + struct anv_state storage_surface_state; + struct anv_state writeonly_storage_surface_state; + + struct brw_image_param storage_image_param; +}; + +struct anv_push_descriptor_set { + struct anv_descriptor_set set; + + /* Put this field right behind anv_descriptor_set so it fills up the + * descriptors[0] field. */ + struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS]; + + struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS]; +}; + struct anv_descriptor_pool { uint32_t size; uint32_t next; @@ -988,6 +947,82 @@ struct anv_descriptor_pool { char data[0]; }; +enum anv_descriptor_template_entry_type { + ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE, + ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER, + ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW +}; + +struct anv_descriptor_template_entry { + /* The type of descriptor in this entry */ + VkDescriptorType type; + + /* Binding in the descriptor set */ + uint32_t binding; + + /* Offset at which to write into the descriptor set binding */ + uint32_t array_element; + + /* Number of elements to write into the descriptor set binding */ + uint32_t array_count; + + /* Offset into the user provided data */ + size_t offset; + + /* Stride between elements into the user provided data */ + size_t stride; +}; + +struct anv_descriptor_update_template { + /* The descriptor set this template corresponds to. This value is only + * valid if the template was created with the templateType + * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR. + */ + uint8_t set; + + /* Number of entries in this template */ + uint32_t entry_count; + + /* Entries of the template */ + struct anv_descriptor_template_entry entries[0]; +}; + +size_t +anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout); + +void +anv_descriptor_set_write_image_view(struct anv_descriptor_set *set, + const struct gen_device_info * const devinfo, + const VkDescriptorImageInfo * const info, + VkDescriptorType type, + uint32_t binding, + uint32_t element); + +void +anv_descriptor_set_write_buffer_view(struct anv_descriptor_set *set, + VkDescriptorType type, + struct anv_buffer_view *buffer_view, + uint32_t binding, + uint32_t element); + +void +anv_descriptor_set_write_buffer(struct anv_descriptor_set *set, + struct anv_device *device, + struct anv_state_stream *alloc_stream, + VkDescriptorType type, + struct anv_buffer *buffer, + uint32_t binding, + uint32_t element, + VkDeviceSize offset, + VkDeviceSize range); + +void +anv_descriptor_set_write_template(struct anv_descriptor_set *set, + struct anv_device *device, + struct anv_state_stream *alloc_stream, + const struct anv_descriptor_update_template *template, + const void *data); + VkResult anv_descriptor_set_create(struct anv_device *device, struct anv_descriptor_pool *pool, @@ -999,17 +1034,26 @@ anv_descriptor_set_destroy(struct anv_device *device, struct anv_descriptor_pool *pool, struct anv_descriptor_set *set); -#define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT16_MAX +#define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX struct anv_pipeline_binding { /* The descriptor set this surface corresponds to. The special value of * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers * to a color attachment and not a regular descriptor. */ - uint16_t set; + uint8_t set; - /* Offset into the descriptor set or attachment list. */ - uint16_t offset; + /* Binding in the descriptor set */ + uint8_t binding; + + /* Index in the binding */ + uint8_t index; + + /* Input attachment index (relative to the subpass) */ + uint8_t input_attachment_index; + + /* For a storage image, whether it is write-only */ + bool write_only; }; struct anv_pipeline_layout { @@ -1023,6 +1067,8 @@ struct anv_pipeline_layout { struct { bool has_dynamic_offsets; } stage[MESA_SHADER_STAGES]; + + unsigned char sha1[20]; }; struct anv_buffer { @@ -1053,6 +1099,45 @@ enum anv_cmd_dirty_bits { }; typedef uint32_t anv_cmd_dirty_mask_t; +enum anv_pipe_bits { + ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0), + ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1), + ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2), + ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3), + ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4), + ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5), + ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10), + ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11), + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12), + ANV_PIPE_DEPTH_STALL_BIT = (1 << 13), + ANV_PIPE_CS_STALL_BIT = (1 << 20), + + /* This bit does not exist directly in PIPE_CONTROL. Instead it means that + * a flush has happened but not a CS stall. The next time we do any sort + * of invalidation we need to insert a CS stall at that time. Otherwise, + * we would have to CS stall on every flush which could be bad. + */ + ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21), +}; + +#define ANV_PIPE_FLUSH_BITS ( \ + ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \ + ANV_PIPE_DATA_CACHE_FLUSH_BIT | \ + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT) + +#define ANV_PIPE_STALL_BITS ( \ + ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \ + ANV_PIPE_DEPTH_STALL_BIT | \ + ANV_PIPE_CS_STALL_BIT) + +#define ANV_PIPE_INVALIDATE_BITS ( \ + ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \ + ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \ + ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \ + ANV_PIPE_DATA_CACHE_FLUSH_BIT | \ + ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \ + ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT) + struct anv_vertex_binding { struct anv_buffer * buffer; VkDeviceSize offset; @@ -1139,18 +1224,27 @@ void anv_dynamic_state_copy(struct anv_dynamic_state *dest, * The clear value is valid only if there exists a pending clear. */ struct anv_attachment_state { + enum isl_aux_usage aux_usage; + enum isl_aux_usage input_aux_usage; + struct anv_state color_rt_state; + struct anv_state input_att_state; + + VkImageLayout current_layout; VkImageAspectFlags pending_clear_aspects; + bool fast_clear; VkClearValue clear_value; + bool clear_color_is_zero_one; }; /** State required while building cmd buffer */ struct anv_cmd_state { /* PIPELINE_SELECT.PipelineSelection */ uint32_t current_pipeline; - uint32_t current_l3_config; + const struct gen_l3_config * current_l3_config; uint32_t vb_dirty; anv_cmd_dirty_mask_t dirty; anv_cmd_dirty_mask_t compute_dirty; + enum anv_pipe_bits pending_pipe_bits; uint32_t num_workgroups_offset; struct anv_bo *num_workgroups_bo; VkShaderStageFlags descriptors_dirty; @@ -1161,21 +1255,52 @@ struct anv_cmd_state { struct anv_framebuffer * framebuffer; struct anv_render_pass * pass; struct anv_subpass * subpass; + VkRect2D render_area; uint32_t restart_index; struct anv_vertex_binding vertex_bindings[MAX_VBS]; struct anv_descriptor_set * descriptors[MAX_SETS]; + VkShaderStageFlags push_constant_stages; struct anv_push_constants * push_constants[MESA_SHADER_STAGES]; struct anv_state binding_tables[MESA_SHADER_STAGES]; struct anv_state samplers[MESA_SHADER_STAGES]; struct anv_dynamic_state dynamic; bool need_query_wa; + struct anv_push_descriptor_set push_descriptor; + + /** + * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top + * of any command buffer it is disabled by disabling it in EndCommandBuffer + * and before invoking the secondary in ExecuteCommands. + */ + bool pma_fix_enabled; + + /** + * Whether or not we know for certain that HiZ is enabled for the current + * subpass. If, for whatever reason, we are unsure as to whether HiZ is + * enabled or not, this will be false. + */ + bool hiz_enabled; + /** * Array length is anv_cmd_state::pass::attachment_count. Array content is * valid only when recording a render pass instance. */ struct anv_attachment_state * attachments; + /** + * Surface states for color render targets. These are stored in a single + * flat array. For depth-stencil attachments, the surface state is simply + * left blank. + */ + struct anv_state render_pass_states; + + /** + * A null surface state of the right size to match the framebuffer. This + * is one of the states in render_pass_states. + */ + struct anv_state null_surface_state; + struct { struct anv_buffer * index_buffer; uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */ @@ -1220,32 +1345,18 @@ struct anv_cmd_buffer { * * initialized by anv_cmd_buffer_init_batch_bo_chain() */ - struct anv_vector seen_bbos; + struct u_vector seen_bbos; /* A vector of int32_t's for every block of binding tables. * * initialized by anv_cmd_buffer_init_batch_bo_chain() */ - struct anv_vector bt_blocks; + struct u_vector bt_blocks; uint32_t bt_next; - struct anv_reloc_list surface_relocs; - - /* Information needed for execbuf - * - * These fields are generated by anv_cmd_buffer_prepare_execbuf(). - */ - struct { - struct drm_i915_gem_execbuffer2 execbuf; - - struct drm_i915_gem_exec_object2 * objects; - uint32_t bo_count; - struct anv_bo ** bos; - - /* Allocated length of the 'objects' and 'bos' arrays */ - uint32_t array_length; - bool need_reloc; - } execbuf2; + struct anv_reloc_list surface_relocs; + /** Last seen surface state block pool center bo offset */ + uint32_t last_ss_pool_center; /* Serial for tracking buffer completion */ uint32_t serial; @@ -1267,14 +1378,18 @@ void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer); void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary, struct anv_cmd_buffer *secondary); void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer); +VkResult anv_cmd_buffer_execbuf(struct anv_device *device, + struct anv_cmd_buffer *cmd_buffer); + +VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer); -VkResult anv_cmd_buffer_emit_binding_table(struct anv_cmd_buffer *cmd_buffer, - unsigned stage, struct anv_state *bt_state); -VkResult anv_cmd_buffer_emit_samplers(struct anv_cmd_buffer *cmd_buffer, - unsigned stage, struct anv_state *state); -uint32_t gen7_cmd_buffer_flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer); -void gen7_cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer *cmd_buffer, - uint32_t stages); +VkResult +anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer, + gl_shader_stage stage, uint32_t size); +#define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \ + anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \ + (offsetof(struct anv_push_constants, field) + \ + sizeof(cmd_buffer->state.push_constants[0]->field))) struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer, const void *data, uint32_t size, uint32_t alignment); @@ -1297,15 +1412,16 @@ VkResult anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer); void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer); +void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer, + bool depth_clamp_enable); void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer); -void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer); - -void anv_cmd_state_setup_attachments(struct anv_cmd_buffer *cmd_buffer, - const VkRenderPassBeginInfo *info); +void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer, + struct anv_render_pass *pass, + struct anv_framebuffer *framebuffer, + const VkClearValue *clear_values); -void anv_cmd_buffer_set_subpass(struct anv_cmd_buffer *cmd_buffer, - struct anv_subpass *subpass); +void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer); struct anv_state anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer, @@ -1319,13 +1435,30 @@ void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer); const struct anv_image_view * anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer); +struct anv_state +anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer, + uint32_t num_entries, + uint32_t *state_offset); + void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer); +enum anv_fence_state { + /** Indicates that this is a new (or newly reset fence) */ + ANV_FENCE_STATE_RESET, + + /** Indicates that this fence has been submitted to the GPU but is still + * (as far as we know) in use by the GPU. + */ + ANV_FENCE_STATE_SUBMITTED, + + ANV_FENCE_STATE_SIGNALED, +}; + struct anv_fence { struct anv_bo bo; struct drm_i915_gem_execbuffer2 execbuf; struct drm_i915_gem_exec_object2 exec2_objects[1]; - bool ready; + enum anv_fence_state state; }; struct anv_event { @@ -1333,11 +1466,7 @@ struct anv_event { struct anv_state state; }; -struct nir_shader; - struct anv_shader_module { - struct nir_shader * nir; - unsigned char sha1[20]; uint32_t size; char data[0]; @@ -1346,6 +1475,7 @@ struct anv_shader_module { void anv_hash_shader(unsigned char *hash, const void *key, size_t key_size, struct anv_shader_module *module, const char *entrypoint, + const struct anv_pipeline_layout *pipeline_layout, const VkSpecializationInfo *spec_info); static inline gl_shader_stage @@ -1373,13 +1503,58 @@ struct anv_pipeline_bind_map { uint32_t surface_count; uint32_t sampler_count; uint32_t image_count; - uint32_t attachment_count; struct anv_pipeline_binding * surface_to_descriptor; struct anv_pipeline_binding * sampler_to_descriptor; - uint32_t * surface_to_attachment; }; +struct anv_shader_bin_key { + uint32_t size; + uint8_t data[0]; +}; + +struct anv_shader_bin { + uint32_t ref_cnt; + + const struct anv_shader_bin_key *key; + + struct anv_state kernel; + uint32_t kernel_size; + + const struct brw_stage_prog_data *prog_data; + uint32_t prog_data_size; + + struct anv_pipeline_bind_map bind_map; + + /* Prog data follows, then params, then the key, all aligned to 8-bytes */ +}; + +struct anv_shader_bin * +anv_shader_bin_create(struct anv_device *device, + const void *key, uint32_t key_size, + const void *kernel, uint32_t kernel_size, + const struct brw_stage_prog_data *prog_data, + uint32_t prog_data_size, const void *prog_data_param, + const struct anv_pipeline_bind_map *bind_map); + +void +anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader); + +static inline void +anv_shader_bin_ref(struct anv_shader_bin *shader) +{ + assert(shader->ref_cnt >= 1); + __sync_fetch_and_add(&shader->ref_cnt, 1); +} + +static inline void +anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader) +{ + assert(shader->ref_cnt >= 1); + if (__sync_fetch_and_add(&shader->ref_cnt, -1) == 1) + anv_shader_bin_destroy(device, shader); +} + struct anv_pipeline { struct anv_device * device; struct anv_batch batch; @@ -1389,32 +1564,18 @@ struct anv_pipeline { struct anv_dynamic_state dynamic_state; struct anv_pipeline_layout * layout; - struct anv_pipeline_bind_map bindings[MESA_SHADER_STAGES]; - bool use_repclear; + bool needs_data_cache; + + struct anv_shader_bin * shaders[MESA_SHADER_STAGES]; - const struct brw_stage_prog_data * prog_data[MESA_SHADER_STAGES]; - uint32_t scratch_start[MESA_SHADER_STAGES]; - uint32_t total_scratch; struct { - uint8_t push_size[MESA_SHADER_FRAGMENT + 1]; - uint32_t start[MESA_SHADER_GEOMETRY + 1]; - uint32_t size[MESA_SHADER_GEOMETRY + 1]; - uint32_t entries[MESA_SHADER_GEOMETRY + 1]; + const struct gen_l3_config * l3_config; + uint32_t total_size; } urb; VkShaderStageFlags active_stages; struct anv_state blend_state; - uint32_t vs_simd8; - uint32_t vs_vec4; - uint32_t ps_simd8; - uint32_t ps_simd16; - uint32_t ps_ksp0; - uint32_t ps_ksp2; - uint32_t ps_grf_start0; - uint32_t ps_grf_start2; - uint32_t gs_kernel; - uint32_t cs_simd; uint32_t vb_used; uint32_t binding_stride[MAX_VBS]; @@ -1422,9 +1583,15 @@ struct anv_pipeline { bool primitive_restart; uint32_t topology; - uint32_t cs_thread_width_max; uint32_t cs_right_mask; + bool writes_depth; + bool depth_test_enable; + bool writes_stencil; + bool stencil_test_enable; + bool depth_clamp_enable; + bool kill_pixel; + struct { uint32_t sf[7]; uint32_t depth_stencil_state[3]; @@ -1439,51 +1606,51 @@ struct anv_pipeline { struct { uint32_t wm_depth_stencil[4]; } gen9; + + uint32_t interface_descriptor_data[8]; }; -static inline const struct brw_vs_prog_data * -get_vs_prog_data(struct anv_pipeline *pipeline) +static inline bool +anv_pipeline_has_stage(const struct anv_pipeline *pipeline, + gl_shader_stage stage) { - return (const struct brw_vs_prog_data *) pipeline->prog_data[MESA_SHADER_VERTEX]; + return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0; } -static inline const struct brw_gs_prog_data * -get_gs_prog_data(struct anv_pipeline *pipeline) -{ - return (const struct brw_gs_prog_data *) pipeline->prog_data[MESA_SHADER_GEOMETRY]; +#define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \ +static inline const struct brw_##prefix##_prog_data * \ +get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \ +{ \ + if (anv_pipeline_has_stage(pipeline, stage)) { \ + return (const struct brw_##prefix##_prog_data *) \ + pipeline->shaders[stage]->prog_data; \ + } else { \ + return NULL; \ + } \ } -static inline const struct brw_wm_prog_data * -get_wm_prog_data(struct anv_pipeline *pipeline) -{ - return (const struct brw_wm_prog_data *) pipeline->prog_data[MESA_SHADER_FRAGMENT]; -} +ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX) +ANV_DECL_GET_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL) +ANV_DECL_GET_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL) +ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY) +ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT) +ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE) -static inline const struct brw_cs_prog_data * -get_cs_prog_data(struct anv_pipeline *pipeline) +static inline const struct brw_vue_prog_data * +anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline *pipeline) { - return (const struct brw_cs_prog_data *) pipeline->prog_data[MESA_SHADER_COMPUTE]; + if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) + return &get_gs_prog_data(pipeline)->base; + else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL)) + return &get_tes_prog_data(pipeline)->base; + else + return &get_vs_prog_data(pipeline)->base; } -struct anv_graphics_pipeline_create_info { - /** - * If non-negative, overrides the color attachment count of the pipeline's - * subpass. - */ - int8_t color_attachment_count; - - bool use_repclear; - bool disable_viewport; - bool disable_scissor; - bool disable_vs; - bool use_rectlist; -}; - VkResult anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device, struct anv_pipeline_cache *cache, const VkGraphicsPipelineCreateInfo *pCreateInfo, - const struct anv_graphics_pipeline_create_info *extra, const VkAllocationCallbacks *alloc); VkResult @@ -1494,54 +1661,45 @@ anv_pipeline_compile_cs(struct anv_pipeline *pipeline, const char *entrypoint, const VkSpecializationInfo *spec_info); -VkResult -anv_graphics_pipeline_create(VkDevice device, - VkPipelineCache cache, - const VkGraphicsPipelineCreateInfo *pCreateInfo, - const struct anv_graphics_pipeline_create_info *extra, - const VkAllocationCallbacks *alloc, - VkPipeline *pPipeline); - -struct anv_format_swizzle { - unsigned r:2; - unsigned g:2; - unsigned b:2; - unsigned a:2; -}; - struct anv_format { - const VkFormat vk_format; - const char *name; - enum isl_format isl_format; /**< RENDER_SURFACE_STATE.SurfaceFormat */ - const struct isl_format_layout *isl_layout; - struct anv_format_swizzle swizzle; - bool has_depth; - bool has_stencil; + enum isl_format isl_format:16; + struct isl_swizzle swizzle; }; -const struct anv_format * -anv_format_for_vk_format(VkFormat format); +struct anv_format +anv_get_format(const struct gen_device_info *devinfo, VkFormat format, + VkImageAspectFlags aspect, VkImageTiling tiling); -enum isl_format -anv_get_isl_format(VkFormat format, VkImageAspectFlags aspect, - VkImageTiling tiling, struct anv_format_swizzle *swizzle); - -static inline bool -anv_format_is_color(const struct anv_format *format) +static inline enum isl_format +anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format, + VkImageAspectFlags aspect, VkImageTiling tiling) { - return !format->has_depth && !format->has_stencil; + return anv_get_format(devinfo, vk_format, aspect, tiling).isl_format; } -static inline bool -anv_format_is_depth_or_stencil(const struct anv_format *format) +static inline struct isl_swizzle +anv_swizzle_for_render(struct isl_swizzle swizzle) { - return format->has_depth || format->has_stencil; + /* Sometimes the swizzle will have alpha map to one. We do this to fake + * RGB as RGBA for texturing + */ + assert(swizzle.a == ISL_CHANNEL_SELECT_ONE || + swizzle.a == ISL_CHANNEL_SELECT_ALPHA); + + /* But it doesn't matter what we render to that channel */ + swizzle.a = ISL_CHANNEL_SELECT_ALPHA; + + return swizzle; } +void +anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm); + /** * Subsurface of an anv_image. */ struct anv_surface { + /** Valid only if isl_surf::size > 0. */ struct isl_surf isl; /** @@ -1556,7 +1714,7 @@ struct anv_image { * of the actual surface formats. */ VkFormat vk_format; - const struct anv_format *format; + VkImageAspectFlags aspects; VkExtent3D extent; uint32_t levels; uint32_t array_size; @@ -1575,7 +1733,7 @@ struct anv_image { * Image subsurfaces * * For each foo, anv_image::foo_surface is valid if and only if - * anv_image::format has a foo aspect. + * anv_image::aspects has a foo aspect. * * The hardware requires that the depth buffer and stencil buffer be * separate surfaces. From Vulkan's perspective, though, depth and stencil @@ -1591,8 +1749,41 @@ struct anv_image { struct anv_surface stencil_surface; }; }; + + /** + * For color images, this is the aux usage for this image when not used as a + * color attachment. + * + * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the image + * has a HiZ buffer. + */ + enum isl_aux_usage aux_usage; + + struct anv_surface aux_surface; }; +/* Returns true if a HiZ-enabled depth buffer can be sampled from. */ +static inline bool +anv_can_sample_with_hiz(const struct gen_device_info * const devinfo, + const VkImageAspectFlags aspect_mask, + const uint32_t samples) +{ + /* Validate the inputs. */ + assert(devinfo && aspect_mask && samples); + return devinfo->gen >= 8 && (aspect_mask & VK_IMAGE_ASPECT_DEPTH_BIT) && + samples == 1; +} + +void +anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer, + const struct anv_image *image, + enum blorp_hiz_op op); + +enum isl_aux_usage +anv_layout_to_aux_usage(const struct gen_device_info * const devinfo, + const struct anv_image *image, + const VkImageAspectFlags aspects, + const VkImageLayout layout); static inline uint32_t anv_get_layerCount(const struct anv_image *image, const VkImageSubresourceRange *range) @@ -1615,27 +1806,38 @@ struct anv_image_view { struct anv_bo *bo; uint32_t offset; /**< Offset into bo. */ + struct isl_view isl; + VkImageAspectFlags aspect_mask; VkFormat vk_format; - uint32_t base_layer; - uint32_t base_mip; VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */ - /** RENDER_SURFACE_STATE when using image as a color render target. */ - struct anv_state color_rt_surface_state; - /** RENDER_SURFACE_STATE when using image as a sampler surface. */ struct anv_state sampler_surface_state; - /** RENDER_SURFACE_STATE when using image as a storage image. */ + /** + * RENDER_SURFACE_STATE when using image as a sampler surface with the + * auxiliary buffer disabled. + */ + struct anv_state no_aux_sampler_surface_state; + + /** + * RENDER_SURFACE_STATE when using image as a storage image. Separate states + * for write-only and readable, using the real format for write-only and the + * lowered format for readable. + */ struct anv_state storage_surface_state; + struct anv_state writeonly_storage_surface_state; struct brw_image_param storage_image_param; }; struct anv_image_create_info { const VkImageCreateInfo *vk_info; + + /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */ isl_tiling_flags_t isl_tiling_flags; + uint32_t stride; }; @@ -1644,31 +1846,12 @@ VkResult anv_image_create(VkDevice _device, const VkAllocationCallbacks* alloc, VkImage *pImage); -struct anv_surface * -anv_image_get_surface_for_aspect_mask(struct anv_image *image, +const struct anv_surface * +anv_image_get_surface_for_aspect_mask(const struct anv_image *image, VkImageAspectFlags aspect_mask); -void anv_image_view_init(struct anv_image_view *view, - struct anv_device *device, - const VkImageViewCreateInfo* pCreateInfo, - struct anv_cmd_buffer *cmd_buffer, - uint32_t offset, - VkImageUsageFlags usage_mask); - -struct anv_buffer_view { - enum isl_format format; /**< VkBufferViewCreateInfo::format */ - struct anv_bo *bo; - uint32_t offset; /**< Offset into bo. */ - uint64_t range; /**< VkBufferViewCreateInfo::range */ - - struct anv_state surface_state; - struct anv_state storage_surface_state; - - struct brw_image_param storage_image_param; -}; - -const struct anv_format * -anv_format_for_descriptor_type(VkDescriptorType type); +enum isl_format +anv_isl_format_for_descriptor_type(VkDescriptorType type); static inline struct VkExtent3D anv_sanitize_image_extent(const VkImageType imageType, @@ -1730,34 +1913,64 @@ struct anv_framebuffer { }; struct anv_subpass { + uint32_t attachment_count; + + /** + * A pointer to all attachment references used in this subpass. + * Only valid if ::attachment_count > 0. + */ + VkAttachmentReference * attachments; uint32_t input_count; - uint32_t * input_attachments; + VkAttachmentReference * input_attachments; uint32_t color_count; - uint32_t * color_attachments; - uint32_t * resolve_attachments; - uint32_t depth_stencil_attachment; + VkAttachmentReference * color_attachments; + VkAttachmentReference * resolve_attachments; + + VkAttachmentReference depth_stencil_attachment; + + /** Subpass has a depth/stencil self-dependency */ + bool has_ds_self_dep; /** Subpass has at least one resolve attachment */ bool has_resolve; }; +enum anv_subpass_usage { + ANV_SUBPASS_USAGE_DRAW = (1 << 0), + ANV_SUBPASS_USAGE_INPUT = (1 << 1), + ANV_SUBPASS_USAGE_RESOLVE_SRC = (1 << 2), + ANV_SUBPASS_USAGE_RESOLVE_DST = (1 << 3), +}; + struct anv_render_pass_attachment { - const struct anv_format *format; + /* TODO: Consider using VkAttachmentDescription instead of storing each of + * its members individually. + */ + VkFormat format; uint32_t samples; + VkImageUsageFlags usage; VkAttachmentLoadOp load_op; + VkAttachmentStoreOp store_op; VkAttachmentLoadOp stencil_load_op; + VkImageLayout initial_layout; + VkImageLayout final_layout; + + /* An array, indexed by subpass id, of how the attachment will be used. */ + enum anv_subpass_usage * subpass_usage; + + /* The subpass id in which the attachment will be used last. */ + uint32_t last_subpass_idx; }; struct anv_render_pass { uint32_t attachment_count; uint32_t subpass_count; - uint32_t * subpass_attachments; + VkAttachmentReference * subpass_attachments; + enum anv_subpass_usage * subpass_usages; struct anv_render_pass_attachment * attachments; struct anv_subpass subpasses[0]; }; -extern struct anv_render_pass anv_meta_dummy_renderpass; - struct anv_query_pool_slot { uint64_t begin; uint64_t end; @@ -1770,14 +1983,38 @@ struct anv_query_pool { struct anv_bo bo; }; -VkResult anv_device_init_meta(struct anv_device *device); -void anv_device_finish_meta(struct anv_device *device); - -void *anv_lookup_entrypoint(const char *name); +void *anv_lookup_entrypoint(const struct gen_device_info *devinfo, + const char *name); void anv_dump_image_to_ppm(struct anv_device *device, struct anv_image *image, unsigned miplevel, - unsigned array_layer, const char *filename); + unsigned array_layer, VkImageAspectFlagBits aspect, + const char *filename); + +enum anv_dump_action { + ANV_DUMP_FRAMEBUFFERS_BIT = 0x1, +}; + +void anv_dump_start(struct anv_device *device, enum anv_dump_action actions); +void anv_dump_finish(void); + +void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer, + struct anv_framebuffer *fb); + +static inline uint32_t +anv_get_subpass_id(const struct anv_cmd_state * const cmd_state) +{ + /* This function must be called from within a subpass. */ + assert(cmd_state->pass && cmd_state->subpass); + + const uint32_t subpass_id = cmd_state->subpass - cmd_state->pass->subpasses; + + /* The id of this subpass shouldn't exceed the number of subpasses in this + * render pass minus 1. + */ + assert(subpass_id < cmd_state->pass->subpass_count); + return subpass_id; +} #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \ \ @@ -1822,6 +2059,7 @@ ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView) ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool) ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet) ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout) +ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template, VkDescriptorUpdateTemplateKHR) ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory) ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence) ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent) @@ -1836,21 +2074,6 @@ ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass) ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler) ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule) -#define ANV_DEFINE_STRUCT_CASTS(__anv_type, __VkType) \ - \ - static inline const __VkType * \ - __anv_type ## _to_ ## __VkType(const struct __anv_type *__anv_obj) \ - { \ - return (const __VkType *) __anv_obj; \ - } - -#define ANV_COMMON_TO_STRUCT(__VkType, __vk_name, __common_name) \ - const __VkType *__vk_name = anv_common_to_ ## __VkType(__common_name) - -ANV_DEFINE_STRUCT_CASTS(anv_common, VkMemoryBarrier) -ANV_DEFINE_STRUCT_CASTS(anv_common, VkBufferMemoryBarrier) -ANV_DEFINE_STRUCT_CASTS(anv_common, VkImageMemoryBarrier) - /* Gen-specific function declarations */ #ifdef genX # include "anv_genX.h" @@ -1869,6 +2092,4 @@ ANV_DEFINE_STRUCT_CASTS(anv_common, VkImageMemoryBarrier) # undef genX #endif -#ifdef __cplusplus -} -#endif +#endif /* ANV_PRIVATE_H */