X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fintel%2Fvulkan%2Fanv_private.h;h=d7934f81d75ebfa001db603b2bbd51761431045a;hb=e02959f442ed6546fb632a153ffc32848968038f;hp=cd24714f93e6b35ba16a2d8efe50d980cab46a8b;hpb=f1654fa7e313a97e8849973b6877700bbdb2ce06;p=mesa.git diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index cd24714f93e..d7934f81d75 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -30,7 +30,7 @@ #include #include #include -#include +#include "drm-uapi/i915_drm.h" #ifdef HAVE_VALGRIND #include @@ -44,6 +44,7 @@ #endif #include "common/gen_clflush.h" +#include "common/gen_decoder.h" #include "common/gen_gem.h" #include "dev/gen_device_info.h" #include "blorp/blorp.h" @@ -151,14 +152,19 @@ struct gen_l3_config; #define ANV_HZ_FC_VAL 1.0f #define MAX_VBS 28 +#define MAX_XFB_BUFFERS 4 +#define MAX_XFB_STREAMS 4 #define MAX_SETS 8 #define MAX_RTS 8 #define MAX_VIEWPORTS 16 #define MAX_SCISSORS 16 #define MAX_PUSH_CONSTANTS_SIZE 128 #define MAX_DYNAMIC_BUFFERS 16 -#define MAX_IMAGES 8 +#define MAX_IMAGES 64 +#define MAX_GEN8_IMAGES 8 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */ +#define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096 +#define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32 /* The kernel relocation API has a limitation of a 32-bit delta value * applied to the address before it is written which, in spite of it being @@ -182,6 +188,11 @@ struct gen_l3_config; #define ANV_SVGS_VB_INDEX MAX_VBS #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1) +/* We reserve this MI ALU register for the purpose of handling predication. + * Other code which uses the MI ALU should leave it alone. + */ +#define ANV_PREDICATE_RESULT_REG MI_ALU_REG15 + #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b))) static inline uint32_t @@ -607,7 +618,7 @@ anv_bo_init(struct anv_bo *bo, uint32_t gem_handle, uint64_t size) */ union anv_free_list { struct { - int32_t offset; + uint32_t offset; /* A simple count that is incremented every time the head changes. */ uint32_t count; @@ -615,7 +626,7 @@ union anv_free_list { uint64_t u64; }; -#define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } }) +#define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } }) struct anv_block_state { union { @@ -627,12 +638,21 @@ struct anv_block_state { }; }; +#define anv_block_pool_foreach_bo(bo, pool) \ + for (bo = (pool)->bos; bo != &(pool)->bos[(pool)->nbos]; bo++) + +#define ANV_MAX_BLOCK_POOL_BOS 20 + struct anv_block_pool { struct anv_device *device; uint64_t bo_flags; - struct anv_bo bo; + struct anv_bo bos[ANV_MAX_BLOCK_POOL_BOS]; + struct anv_bo *bo; + uint32_t nbos; + + uint64_t size; /* The address where the start of the pool is pinned. The various bos that * are created as the pool grows will have addresses in the range @@ -654,6 +674,9 @@ struct anv_block_pool { * will be valid relative to this pointer. * * In particular, map == bo.map + center_offset + * + * DO NOT access this pointer directly. Use anv_block_pool_map() instead, + * since it will handle the softpin case as well, where this points to NULL. */ void *map; int fd; @@ -687,6 +710,7 @@ struct anv_state { int32_t offset; uint32_t alloc_size; void *map; + uint32_t idx; }; #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 }) @@ -701,9 +725,25 @@ struct anv_fixed_size_state_pool { #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1) +struct anv_free_entry { + uint32_t next; + struct anv_state state; +}; + +struct anv_state_table { + struct anv_device *device; + int fd; + struct anv_free_entry *map; + uint32_t size; + struct anv_block_state state; + struct u_vector mmap_cleanups; +}; + struct anv_state_pool { struct anv_block_pool block_pool; + struct anv_state_table table; + /* The size of blocks which will be allocated from the block pool */ uint32_t block_size; @@ -741,9 +781,10 @@ VkResult anv_block_pool_init(struct anv_block_pool *pool, uint64_t bo_flags); void anv_block_pool_finish(struct anv_block_pool *pool); int32_t anv_block_pool_alloc(struct anv_block_pool *pool, - uint32_t block_size); + uint32_t block_size, uint32_t *padding); int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool, uint32_t block_size); +void* anv_block_pool_map(struct anv_block_pool *pool, int32_t offset); VkResult anv_state_pool_init(struct anv_state_pool *pool, struct anv_device *device, @@ -762,6 +803,24 @@ void anv_state_stream_finish(struct anv_state_stream *stream); struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream, uint32_t size, uint32_t alignment); +VkResult anv_state_table_init(struct anv_state_table *table, + struct anv_device *device, + uint32_t initial_entries); +void anv_state_table_finish(struct anv_state_table *table); +VkResult anv_state_table_add(struct anv_state_table *table, uint32_t *idx, + uint32_t count); +void anv_free_list_push(union anv_free_list *list, + struct anv_state_table *table, + uint32_t idx, uint32_t count); +struct anv_state* anv_free_list_pop(union anv_free_list *list, + struct anv_state_table *table); + + +static inline struct anv_state * +anv_state_table_get(struct anv_state_table *table, uint32_t idx) +{ + return &table->map[idx].state; +} /** * Implements a pool of re-usable BOs. The interface is identical to that * of block_pool except that each block is its own BO. @@ -812,6 +871,10 @@ VkResult anv_bo_cache_alloc(struct anv_device *device, struct anv_bo_cache *cache, uint64_t size, uint64_t bo_flags, struct anv_bo **bo); +VkResult anv_bo_cache_import_host_ptr(struct anv_device *device, + struct anv_bo_cache *cache, + void *host_ptr, uint32_t size, + uint64_t bo_flags, struct anv_bo **bo_out); VkResult anv_bo_cache_import(struct anv_device *device, struct anv_bo_cache *cache, int fd, uint64_t bo_flags, @@ -947,9 +1010,12 @@ struct anv_pipeline_cache { struct anv_device * device; pthread_mutex_t mutex; + struct hash_table * nir_cache; + struct hash_table * cache; }; +struct nir_xfb_info; struct anv_pipeline_bind_map; void anv_pipeline_cache_init(struct anv_pipeline_cache *cache, @@ -968,6 +1034,7 @@ anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache, uint32_t constant_data_size, const struct brw_stage_prog_data *prog_data, uint32_t prog_data_size, + const struct nir_xfb_info *xfb_info, const struct anv_pipeline_bind_map *bind_map); struct anv_shader_bin * @@ -984,8 +1051,25 @@ anv_device_upload_kernel(struct anv_device *device, uint32_t constant_data_size, const struct brw_stage_prog_data *prog_data, uint32_t prog_data_size, + const struct nir_xfb_info *xfb_info, const struct anv_pipeline_bind_map *bind_map); +struct nir_shader; +struct nir_shader_compiler_options; + +struct nir_shader * +anv_device_search_for_nir(struct anv_device *device, + struct anv_pipeline_cache *cache, + const struct nir_shader_compiler_options *nir_options, + unsigned char sha1_key[20], + void *mem_ctx); + +void +anv_device_upload_nir(struct anv_device *device, + struct anv_pipeline_cache *cache, + const struct nir_shader *nir, + unsigned char sha1_key[20]); + struct anv_device { VK_LOADER_DATA _loader_data; @@ -1022,6 +1106,12 @@ struct anv_device { struct anv_bo trivial_batch_bo; struct anv_bo hiz_clear_bo; + /* Set of pointers to anv_buffer objects for all pinned buffers. Pinned + * buffers are always resident because they could be used at any time via + * VK_EXT_buffer_device_address. + */ + struct set * pinned_buffers; + struct anv_pipeline_cache default_pipeline_cache; struct blorp_context blorp; @@ -1037,6 +1127,13 @@ struct anv_device { pthread_mutex_t mutex; pthread_cond_t queue_submit; bool _lost; + + struct gen_batch_decode_ctx decoder_ctx; + /* + * When decoding a anv_cmd_buffer, we might need to search for BOs through + * the cmd_buffer's list. + */ + struct anv_cmd_buffer *cmd_buffer_being_decoded; }; static inline struct anv_state_pool * @@ -1071,15 +1168,6 @@ anv_mocs_for_bo(const struct anv_device *device, const struct anv_bo *bo) return device->default_mocs; } -static void inline -anv_state_flush(struct anv_device *device, struct anv_state state) -{ - if (device->info.has_llc) - return; - - gen_flush_range(state.map, state.alloc_size); -} - void anv_device_init_blorp(struct anv_device *device); void anv_device_finish_blorp(struct anv_device *device); @@ -1381,10 +1469,10 @@ _anv_combine_address(struct anv_batch *batch, void *location, */ /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ -#define GEN9_MOCS 2 +#define GEN9_MOCS (2 << 1) /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ -#define GEN9_EXTERNAL_MOCS 1 +#define GEN9_EXTERNAL_MOCS (1 << 1) /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */ #define GEN10_MOCS GEN9_MOCS @@ -1404,6 +1492,9 @@ struct anv_device_memory { * which we must release when memory is freed. */ struct AHardwareBuffer * ahw; + + /* If set, this memory comes from a host pointer. */ + void * host_ptr; }; /** @@ -1416,13 +1507,31 @@ struct anv_vue_header { float PointWidth; }; +enum anv_descriptor_data { + /** The descriptor contains a BTI reference to a surface state */ + ANV_DESCRIPTOR_SURFACE_STATE = (1 << 0), + /** The descriptor contains a BTI reference to a sampler state */ + ANV_DESCRIPTOR_SAMPLER_STATE = (1 << 1), + /** The descriptor contains an actual buffer view */ + ANV_DESCRIPTOR_BUFFER_VIEW = (1 << 2), + /** The descriptor contains auxiliary image layout data */ + ANV_DESCRIPTOR_IMAGE_PARAM = (1 << 3), + /** The descriptor contains auxiliary image layout data */ + ANV_DESCRIPTOR_INLINE_UNIFORM = (1 << 4), +}; + struct anv_descriptor_set_binding_layout { #ifndef NDEBUG /* The type of the descriptors in this binding */ VkDescriptorType type; #endif - /* Number of array elements in this binding */ + /* Bitfield representing the type of data this descriptor contains */ + enum anv_descriptor_data data; + + /* Number of array elements in this binding (or size in bytes for inline + * uniform data) + */ uint16_t array_size; /* Index into the flattend descriptor set */ @@ -1432,23 +1541,20 @@ struct anv_descriptor_set_binding_layout { int16_t dynamic_offset_index; /* Index into the descriptor set buffer views */ - int16_t buffer_index; + int16_t buffer_view_index; - struct { - /* Index into the binding table for the associated surface */ - int16_t surface_index; - - /* Index into the sampler table for the associated sampler */ - int16_t sampler_index; - - /* Index into the image table for the associated image */ - int16_t image_index; - } stage[MESA_SHADER_STAGES]; + /* Offset into the descriptor buffer where this descriptor lives */ + uint32_t descriptor_offset; /* Immutable samplers (or NULL if no immutable samplers) */ struct anv_sampler **immutable_samplers; }; +unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout *layout); + +unsigned anv_descriptor_type_size(const struct anv_physical_device *pdevice, + VkDescriptorType type); + struct anv_descriptor_set_layout { /* Descriptor set layouts can be destroyed at almost any time */ uint32_t ref_cnt; @@ -1462,12 +1568,15 @@ struct anv_descriptor_set_layout { /* Shader stages affected by this descriptor set */ uint16_t shader_stages; - /* Number of buffers in this descriptor set */ - uint16_t buffer_count; + /* Number of buffer views in this descriptor set */ + uint16_t buffer_view_count; /* Number of dynamic offsets used by this descriptor set */ uint16_t dynamic_offset_count; + /* Size of the descriptor buffer for this descriptor set */ + uint32_t descriptor_buffer_size; + /* Bindings in this descriptor set */ struct anv_descriptor_set_binding_layout binding[0]; }; @@ -1509,9 +1618,16 @@ struct anv_descriptor { }; struct anv_descriptor_set { + struct anv_descriptor_pool *pool; struct anv_descriptor_set_layout *layout; uint32_t size; - uint32_t buffer_count; + + /* State relative to anv_descriptor_pool::bo */ + struct anv_state desc_mem; + /* Surface state for the descriptor buffer */ + struct anv_state desc_surface_state; + + uint32_t buffer_view_count; struct anv_buffer_view *buffer_views; struct anv_descriptor descriptors[0]; }; @@ -1535,6 +1651,12 @@ struct anv_push_descriptor_set { /* Put this field right behind anv_descriptor_set so it fills up the * descriptors[0] field. */ struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS]; + + /** True if the descriptor set buffer has been referenced by a draw or + * dispatch command. + */ + bool set_used_on_gpu; + struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS]; }; @@ -1543,6 +1665,9 @@ struct anv_descriptor_pool { uint32_t next; uint32_t free_list; + struct anv_bo bo; + struct util_vma_heap bo_heap; + struct anv_state_stream surface_state_stream; void *surface_state_free_list; @@ -1580,7 +1705,7 @@ struct anv_descriptor_update_template { /* The descriptor set this template corresponds to. This value is only * valid if the template was created with the templateType - * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR. + * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET. */ uint8_t set; @@ -1595,23 +1720,24 @@ size_t anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout); void -anv_descriptor_set_write_image_view(struct anv_descriptor_set *set, - const struct gen_device_info * const devinfo, +anv_descriptor_set_write_image_view(struct anv_device *device, + struct anv_descriptor_set *set, const VkDescriptorImageInfo * const info, VkDescriptorType type, uint32_t binding, uint32_t element); void -anv_descriptor_set_write_buffer_view(struct anv_descriptor_set *set, +anv_descriptor_set_write_buffer_view(struct anv_device *device, + struct anv_descriptor_set *set, VkDescriptorType type, struct anv_buffer_view *buffer_view, uint32_t binding, uint32_t element); void -anv_descriptor_set_write_buffer(struct anv_descriptor_set *set, - struct anv_device *device, +anv_descriptor_set_write_buffer(struct anv_device *device, + struct anv_descriptor_set *set, struct anv_state_stream *alloc_stream, VkDescriptorType type, struct anv_buffer *buffer, @@ -1619,10 +1745,17 @@ anv_descriptor_set_write_buffer(struct anv_descriptor_set *set, uint32_t element, VkDeviceSize offset, VkDeviceSize range); +void +anv_descriptor_set_write_inline_uniform_data(struct anv_device *device, + struct anv_descriptor_set *set, + uint32_t binding, + const void *data, + size_t offset, + size_t size); void -anv_descriptor_set_write_template(struct anv_descriptor_set *set, - struct anv_device *device, +anv_descriptor_set_write_template(struct anv_device *device, + struct anv_descriptor_set *set, struct anv_state_stream *alloc_stream, const struct anv_descriptor_update_template *template, const void *data); @@ -1638,6 +1771,8 @@ anv_descriptor_set_destroy(struct anv_device *device, struct anv_descriptor_pool *pool, struct anv_descriptor_set *set); +#define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3) +#define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2) #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1) #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX @@ -1672,10 +1807,6 @@ struct anv_pipeline_layout { uint32_t num_sets; - struct { - bool has_dynamic_offsets; - } stage[MESA_SHADER_STAGES]; - unsigned char sha1[20]; }; @@ -1716,6 +1847,7 @@ enum anv_cmd_dirty_bits { ANV_CMD_DIRTY_PIPELINE = 1 << 9, ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10, ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11, + ANV_CMD_DIRTY_XFB_ENABLE = 1 << 12, }; typedef uint32_t anv_cmd_dirty_mask_t; @@ -1740,11 +1872,12 @@ enum anv_pipe_bits { ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21), /* This bit does not exist directly in PIPE_CONTROL. It means that render - * target operations are ongoing. Some operations like copies on the - * command streamer might need to be aware of this to trigger the - * appropriate stall before they can proceed with the copy. + * target operations related to transfer commands with VkBuffer as + * destination are ongoing. Some operations like copies on the command + * streamer might need to be aware of this to trigger the appropriate stall + * before they can proceed with the copy. */ - ANV_PIPE_RENDER_TARGET_WRITES = (1 << 22), + ANV_PIPE_RENDER_TARGET_BUFFER_WRITES = (1 << 22), }; #define ANV_PIPE_FLUSH_BITS ( \ @@ -1774,19 +1907,47 @@ anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags) for_each_bit(b, flags) { switch ((VkAccessFlagBits)(1 << b)) { case VK_ACCESS_SHADER_WRITE_BIT: + /* We're transitioning a buffer that was previously used as write + * destination through the data port. To make its content available + * to future operations, flush the data cache. + */ pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT; break; case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT: + /* We're transitioning a buffer that was previously used as render + * target. To make its content available to future operations, flush + * the render target cache. + */ pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT; break; case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT: + /* We're transitioning a buffer that was previously used as depth + * buffer. To make its content available to future operations, flush + * the depth cache. + */ pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT; break; case VK_ACCESS_TRANSFER_WRITE_BIT: + /* We're transitioning a buffer that was previously used as a + * transfer write destination. Generic write operations include color + * & depth operations as well as buffer operations like : + * - vkCmdClearColorImage() + * - vkCmdClearDepthStencilImage() + * - vkCmdBlitImage() + * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*() + * + * Most of these operations are implemented using Blorp which writes + * through the render target, so flush that cache to make it visible + * to future operations. And for depth related operations we also + * need to flush the depth cache. + */ pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT; pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT; break; case VK_ACCESS_MEMORY_WRITE_BIT: + /* We're transitioning a buffer for generic write operations. Flush + * all the caches. + */ pipe_bits |= ANV_PIPE_FLUSH_BITS; break; default: @@ -1806,25 +1967,67 @@ anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags) for_each_bit(b, flags) { switch ((VkAccessFlagBits)(1 << b)) { case VK_ACCESS_INDIRECT_COMMAND_READ_BIT: + /* Indirect draw commands take a buffer as input that we're going to + * read from the command streamer to load some of the HW registers + * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a + * command streamer stall so that all the cache flushes have + * completed before the command streamer loads from memory. + */ + pipe_bits |= ANV_PIPE_CS_STALL_BIT; + /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex + * through a vertex buffer, so invalidate that cache. + */ + pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT; + /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a + * UBO from the buffer, so we need to invalidate constant cache. + */ + pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT; + break; case VK_ACCESS_INDEX_READ_BIT: case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT: + /* We transitioning a buffer to be used for as input for vkCmdDraw* + * commands, so we invalidate the VF cache to make sure there is no + * stale data when we start rendering. + */ pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT; break; case VK_ACCESS_UNIFORM_READ_BIT: + /* We transitioning a buffer to be used as uniform data. Because + * uniform is accessed through the data port & sampler, we need to + * invalidate the texture cache (sampler) & constant cache (data + * port) to avoid stale data. + */ pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT; pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT; break; case VK_ACCESS_SHADER_READ_BIT: case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT: case VK_ACCESS_TRANSFER_READ_BIT: + /* Transitioning a buffer to be read through the sampler, so + * invalidate the texture cache, we don't want any stale data. + */ pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT; break; case VK_ACCESS_MEMORY_READ_BIT: + /* Transitioning a buffer for generic read, invalidate all the + * caches. + */ pipe_bits |= ANV_PIPE_INVALIDATE_BITS; break; case VK_ACCESS_MEMORY_WRITE_BIT: + /* Generic write, make sure all previously written things land in + * memory. + */ pipe_bits |= ANV_PIPE_FLUSH_BITS; break; + case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT: + /* Transitioning a buffer for conditional rendering. We'll load the + * content of this buffer into HW registers using the command + * streamer, so we need to stall the command streamer to make sure + * any in-flight flush operations have completed. + */ + pipe_bits |= ANV_PIPE_CS_STALL_BIT; + break; default: break; /* Nothing to do */ } @@ -1848,6 +2051,12 @@ struct anv_vertex_binding { VkDeviceSize offset; }; +struct anv_xfb_binding { + struct anv_buffer * buffer; + VkDeviceSize offset; + VkDeviceSize size; +}; + #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset)) #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff) @@ -1865,7 +2074,7 @@ struct anv_push_constants { uint32_t base_work_group_id[3]; /* Image data for image_load_store on pre-SKL */ - struct brw_image_param images[MAX_IMAGES]; + struct brw_image_param images[MAX_GEN8_IMAGES]; }; struct anv_dynamic_state { @@ -2040,6 +2249,8 @@ struct anv_cmd_state { VkRect2D render_area; uint32_t restart_index; struct anv_vertex_binding vertex_bindings[MAX_VBS]; + bool xfb_enabled; + struct anv_xfb_binding xfb_bindings[MAX_XFB_BUFFERS]; VkShaderStageFlags push_constant_stages; struct anv_push_constants * push_constants[MESA_SHADER_STAGES]; struct anv_state binding_tables[MESA_SHADER_STAGES]; @@ -2059,6 +2270,8 @@ struct anv_cmd_state { */ bool hiz_enabled; + bool conditional_render_enabled; + /** * Array length is anv_cmd_state::pass::attachment_count. Array content is * valid only when recording a render pass instance. @@ -2205,8 +2418,6 @@ anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer, struct anv_state anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer); -void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer); - const struct anv_image_view * anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer); @@ -2218,6 +2429,8 @@ anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer, void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer); +void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer *cmd_buffer); + enum anv_fence_type { ANV_FENCE_TYPE_NONE = 0, ANV_FENCE_TYPE_BO, @@ -2369,7 +2582,7 @@ mesa_to_vk_shader_stage(gl_shader_stage mesa_stage) struct anv_pipeline_bind_map { uint32_t surface_count; uint32_t sampler_count; - uint32_t image_count; + uint32_t image_param_count; struct anv_pipeline_binding * surface_to_descriptor; struct anv_pipeline_binding * sampler_to_descriptor; @@ -2394,6 +2607,8 @@ struct anv_shader_bin { const struct brw_stage_prog_data *prog_data; uint32_t prog_data_size; + struct nir_xfb_info *xfb_info; + struct anv_pipeline_bind_map bind_map; }; @@ -2404,6 +2619,7 @@ anv_shader_bin_create(struct anv_device *device, const void *constant_data, uint32_t constant_data_size, const struct brw_stage_prog_data *prog_data, uint32_t prog_data_size, const void *prog_data_param, + const struct nir_xfb_info *xfb_info, const struct anv_pipeline_bind_map *bind_map); void @@ -2453,6 +2669,8 @@ struct anv_pipeline { uint32_t instance_divisor; } vb[MAX_VBS]; + uint8_t xfb_used; + bool primitive_restart; uint32_t topology; @@ -2463,6 +2681,7 @@ struct anv_pipeline { bool writes_stencil; bool stencil_test_enable; bool depth_clamp_enable; + bool depth_clip_enable; bool sample_shading_enable; bool kill_pixel; @@ -2555,6 +2774,7 @@ struct anv_format_plane { struct anv_format { struct anv_format_plane planes[3]; + VkFormat vk_format; uint8_t n_planes; bool can_ycbcr; }; @@ -2922,6 +3142,20 @@ anv_image_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer, VkRect2D area, float depth_value, uint8_t stencil_value); void +anv_image_msaa_resolve(struct anv_cmd_buffer *cmd_buffer, + const struct anv_image *src_image, + enum isl_aux_usage src_aux_usage, + uint32_t src_level, uint32_t src_base_layer, + const struct anv_image *dst_image, + enum isl_aux_usage dst_aux_usage, + uint32_t dst_level, uint32_t dst_base_layer, + VkImageAspectFlagBits aspect, + uint32_t src_x, uint32_t src_y, + uint32_t dst_x, uint32_t dst_y, + uint32_t width, uint32_t height, + uint32_t layer_count, + enum blorp_filter filter); +void anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer, const struct anv_image *image, VkImageAspectFlagBits aspect, uint32_t level, @@ -2937,6 +3171,7 @@ anv_image_hiz_clear(struct anv_cmd_buffer *cmd_buffer, void anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer, const struct anv_image *image, + enum isl_format format, VkImageAspectFlagBits aspect, uint32_t base_layer, uint32_t layer_count, enum isl_aux_op mcs_op, union isl_color_value *clear_value, @@ -2944,6 +3179,7 @@ anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer, void anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer, const struct anv_image *image, + enum isl_format format, VkImageAspectFlagBits aspect, uint32_t level, uint32_t base_layer, uint32_t layer_count, enum isl_aux_op ccs_op, union isl_color_value *clear_value, @@ -3202,14 +3438,17 @@ struct anv_subpass { struct anv_subpass_attachment * resolve_attachments; struct anv_subpass_attachment * depth_stencil_attachment; + struct anv_subpass_attachment * ds_resolve_attachment; + VkResolveModeFlagBitsKHR depth_resolve_mode; + VkResolveModeFlagBitsKHR stencil_resolve_mode; uint32_t view_mask; /** Subpass has a depth/stencil self-dependency */ bool has_ds_self_dep; - /** Subpass has at least one resolve attachment */ - bool has_resolve; + /** Subpass has at least one color resolve attachment */ + bool has_color_resolve; }; static inline unsigned @@ -3345,7 +3584,7 @@ ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView) ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool) ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet) ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout) -ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template, VkDescriptorUpdateTemplateKHR) +ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template, VkDescriptorUpdateTemplate) ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory) ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence) ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)