X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fintel%2Fvulkan%2Fgen7_cmd_buffer.c;h=4977cc97aae5ed1a5690b907fee3ae106c3063ae;hb=4d44848c470c9d214c03906d8decd8056829c4ce;hp=b1721c78ba0c732365856b02cb642e5fd15fbcca;hpb=a316d8f406080cbfe516c7deaf52968de2eadfed;p=mesa.git diff --git a/src/intel/vulkan/gen7_cmd_buffer.c b/src/intel/vulkan/gen7_cmd_buffer.c index b1721c78ba0..4977cc97aae 100644 --- a/src/intel/vulkan/gen7_cmd_buffer.c +++ b/src/intel/vulkan/gen7_cmd_buffer.c @@ -33,7 +33,8 @@ #include "genxml/gen_macros.h" #include "genxml/genX_pack.h" -static inline int64_t +#if GEN_GEN == 7 && !GEN_IS_HASWELL +static int64_t clamp_int64(int64_t x, int64_t min, int64_t max) { if (x < min) @@ -44,12 +45,12 @@ clamp_int64(int64_t x, int64_t min, int64_t max) return max; } -#if GEN_GEN == 7 && !GEN_IS_HASWELL void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer) { - uint32_t count = cmd_buffer->state.dynamic.scissor.count; - const VkRect2D *scissors = cmd_buffer->state.dynamic.scissor.scissors; + struct anv_framebuffer *fb = cmd_buffer->state.framebuffer; + uint32_t count = cmd_buffer->state.gfx.dynamic.scissor.count; + const VkRect2D *scissors = cmd_buffer->state.gfx.dynamic.scissor.scissors; struct anv_state scissor_state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32); @@ -69,12 +70,36 @@ gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer) }; const int max = 0xffff; + + uint32_t y_min = s->offset.y; + uint32_t x_min = s->offset.x; + uint32_t y_max = s->offset.y + s->extent.height - 1; + uint32_t x_max = s->offset.x + s->extent.width - 1; + + /* Do this math using int64_t so overflow gets clamped correctly. */ + if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) { + y_min = clamp_int64((uint64_t) y_min, + cmd_buffer->state.render_area.offset.y, max); + x_min = clamp_int64((uint64_t) x_min, + cmd_buffer->state.render_area.offset.x, max); + y_max = clamp_int64((uint64_t) y_max, 0, + cmd_buffer->state.render_area.offset.y + + cmd_buffer->state.render_area.extent.height - 1); + x_max = clamp_int64((uint64_t) x_max, 0, + cmd_buffer->state.render_area.offset.x + + cmd_buffer->state.render_area.extent.width - 1); + } else if (fb) { + y_min = clamp_int64((uint64_t) y_min, 0, max); + x_min = clamp_int64((uint64_t) x_min, 0, max); + y_max = clamp_int64((uint64_t) y_max, 0, fb->height - 1); + x_max = clamp_int64((uint64_t) x_max, 0, fb->width - 1); + } + struct GEN7_SCISSOR_RECT scissor = { - /* Do this math using int64_t so overflow gets clamped correctly. */ - .ScissorRectangleYMin = clamp_int64(s->offset.y, 0, max), - .ScissorRectangleXMin = clamp_int64(s->offset.x, 0, max), - .ScissorRectangleYMax = clamp_int64((uint64_t) s->offset.y + s->extent.height - 1, 0, max), - .ScissorRectangleXMax = clamp_int64((uint64_t) s->offset.x + s->extent.width - 1, 0, max) + .ScissorRectangleYMin = y_min, + .ScissorRectangleXMin = x_min, + .ScissorRectangleYMax = y_max, + .ScissorRectangleXMax = x_max }; if (s->extent.width <= 0 || s->extent.height <= 0) { @@ -89,20 +114,36 @@ gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer) GEN7_3DSTATE_SCISSOR_STATE_POINTERS, ssp) { ssp.ScissorRectPointer = scissor_state.offset; } - - anv_state_flush(cmd_buffer->device, scissor_state); } #endif -static const uint32_t vk_to_gen_index_type[] = { - [VK_INDEX_TYPE_UINT16] = INDEX_WORD, - [VK_INDEX_TYPE_UINT32] = INDEX_DWORD, -}; +static uint32_t vk_to_gen_index_type(VkIndexType type) +{ + switch (type) { + case VK_INDEX_TYPE_UINT8_EXT: + return INDEX_BYTE; + case VK_INDEX_TYPE_UINT16: + return INDEX_WORD; + case VK_INDEX_TYPE_UINT32: + return INDEX_DWORD; + default: + unreachable("invalid index type"); + } +} -static const uint32_t restart_index_for_type[] = { - [VK_INDEX_TYPE_UINT16] = UINT16_MAX, - [VK_INDEX_TYPE_UINT32] = UINT32_MAX, -}; +static uint32_t restart_index_for_type(VkIndexType type) +{ + switch (type) { + case VK_INDEX_TYPE_UINT8_EXT: + return UINT8_MAX; + case VK_INDEX_TYPE_UINT16: + return UINT16_MAX; + case VK_INDEX_TYPE_UINT32: + return UINT32_MAX; + default: + unreachable("invalid index type"); + } +} void genX(CmdBindIndexBuffer)( VkCommandBuffer commandBuffer, @@ -113,12 +154,12 @@ void genX(CmdBindIndexBuffer)( ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer); ANV_FROM_HANDLE(anv_buffer, buffer, _buffer); - cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER; + cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER; if (GEN_IS_HASWELL) - cmd_buffer->state.restart_index = restart_index_for_type[indexType]; - cmd_buffer->state.gen7.index_buffer = buffer; - cmd_buffer->state.gen7.index_type = vk_to_gen_index_type[indexType]; - cmd_buffer->state.gen7.index_offset = offset; + cmd_buffer->state.restart_index = restart_index_for_type(indexType); + cmd_buffer->state.gfx.gen7.index_buffer = buffer; + cmd_buffer->state.gfx.gen7.index_type = vk_to_gen_index_type(indexType); + cmd_buffer->state.gfx.gen7.index_offset = offset; } static uint32_t @@ -127,11 +168,11 @@ get_depth_format(struct anv_cmd_buffer *cmd_buffer) const struct anv_render_pass *pass = cmd_buffer->state.pass; const struct anv_subpass *subpass = cmd_buffer->state.subpass; - if (subpass->depth_stencil_attachment.attachment >= pass->attachment_count) + if (!subpass->depth_stencil_attachment) return D16_UNORM; struct anv_render_pass_attachment *att = - &pass->attachments[subpass->depth_stencil_attachment.attachment]; + &pass->attachments[subpass->depth_stencil_attachment->attachment]; switch (att->format) { case VK_FORMAT_D16_UNORM: @@ -154,55 +195,62 @@ get_depth_format(struct anv_cmd_buffer *cmd_buffer) void genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) { - struct anv_pipeline *pipeline = cmd_buffer->state.pipeline; + struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline; + struct anv_dynamic_state *d = &cmd_buffer->state.gfx.dynamic; - if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE | - ANV_CMD_DIRTY_RENDER_TARGETS | - ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | - ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) { + if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE | + ANV_CMD_DIRTY_RENDER_TARGETS | + ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | + ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) { uint32_t sf_dw[GENX(3DSTATE_SF_length)]; struct GENX(3DSTATE_SF) sf = { GENX(3DSTATE_SF_header), .DepthBufferSurfaceFormat = get_depth_format(cmd_buffer), - .LineWidth = cmd_buffer->state.dynamic.line_width, - .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias, - .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope, - .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp + .LineWidth = d->line_width, + .GlobalDepthOffsetConstant = d->depth_bias.bias, + .GlobalDepthOffsetScale = d->depth_bias.slope, + .GlobalDepthOffsetClamp = d->depth_bias.clamp }; GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf); anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf); } - if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | - ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) { - struct anv_dynamic_state *d = &cmd_buffer->state.dynamic; + if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | + ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) { struct anv_state cc_state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, GENX(COLOR_CALC_STATE_length) * 4, 64); struct GENX(COLOR_CALC_STATE) cc = { - .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0], - .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1], - .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2], - .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3], + .BlendConstantColorRed = d->blend_constants[0], + .BlendConstantColorGreen = d->blend_constants[1], + .BlendConstantColorBlue = d->blend_constants[2], + .BlendConstantColorAlpha = d->blend_constants[3], .StencilReferenceValue = d->stencil_reference.front & 0xff, .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff, }; GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc); - anv_state_flush(cmd_buffer->device, cc_state); anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) { ccp.ColorCalcStatePointer = cc_state.offset; } } - if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE | - ANV_CMD_DIRTY_RENDER_TARGETS | - ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | - ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) { + if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE) { + anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_LINE_STIPPLE), ls) { + ls.LineStipplePattern = d->line_stipple.pattern; + ls.LineStippleInverseRepeatCount = + 1.0f / MAX2(1, d->line_stipple.factor); + ls.LineStippleRepeatCount = d->line_stipple.factor; + } + } + + if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE | + ANV_CMD_DIRTY_RENDER_TARGETS | + ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | + ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) { uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)]; - struct anv_dynamic_state *d = &cmd_buffer->state.dynamic; struct GENX(DEPTH_STENCIL_STATE) depth_stencil = { .StencilTestMask = d->stencil_compare_mask.front & 0xff, @@ -228,11 +276,11 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) } } - if (cmd_buffer->state.gen7.index_buffer && - cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE | - ANV_CMD_DIRTY_INDEX_BUFFER)) { - struct anv_buffer *buffer = cmd_buffer->state.gen7.index_buffer; - uint32_t offset = cmd_buffer->state.gen7.index_offset; + if (cmd_buffer->state.gfx.gen7.index_buffer && + cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE | + ANV_CMD_DIRTY_INDEX_BUFFER)) { + struct anv_buffer *buffer = cmd_buffer->state.gfx.gen7.index_buffer; + uint32_t offset = cmd_buffer->state.gfx.gen7.index_offset; #if GEN_IS_HASWELL anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF, vf) { @@ -245,17 +293,18 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) #if !GEN_IS_HASWELL ib.CutIndexEnable = pipeline->primitive_restart; #endif - ib.IndexFormat = cmd_buffer->state.gen7.index_type; - ib.MemoryObjectControlState = GENX(MOCS); - - ib.BufferStartingAddress = - (struct anv_address) { buffer->bo, buffer->offset + offset }; - ib.BufferEndingAddress = - (struct anv_address) { buffer->bo, buffer->offset + buffer->size }; + ib.IndexFormat = cmd_buffer->state.gfx.gen7.index_type; + ib.MOCS = anv_mocs_for_bo(cmd_buffer->device, + buffer->address.bo); + + ib.BufferStartingAddress = anv_address_add(buffer->address, + offset); + ib.BufferEndingAddress = anv_address_add(buffer->address, + buffer->size); } } - cmd_buffer->state.dirty = 0; + cmd_buffer->state.gfx.dirty = 0; } void @@ -264,41 +313,3 @@ genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, { /* The NP PMA fix doesn't exist on gen7 */ } - -void genX(CmdSetEvent)( - VkCommandBuffer commandBuffer, - VkEvent event, - VkPipelineStageFlags stageMask) -{ - anv_finishme("Implement events on gen7"); -} - -void genX(CmdResetEvent)( - VkCommandBuffer commandBuffer, - VkEvent event, - VkPipelineStageFlags stageMask) -{ - anv_finishme("Implement events on gen7"); -} - -void genX(CmdWaitEvents)( - VkCommandBuffer commandBuffer, - uint32_t eventCount, - const VkEvent* pEvents, - VkPipelineStageFlags srcStageMask, - VkPipelineStageFlags destStageMask, - uint32_t memoryBarrierCount, - const VkMemoryBarrier* pMemoryBarriers, - uint32_t bufferMemoryBarrierCount, - const VkBufferMemoryBarrier* pBufferMemoryBarriers, - uint32_t imageMemoryBarrierCount, - const VkImageMemoryBarrier* pImageMemoryBarriers) -{ - anv_finishme("Implement events on gen7"); - - genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask, - false, /* byRegion */ - memoryBarrierCount, pMemoryBarriers, - bufferMemoryBarrierCount, pBufferMemoryBarriers, - imageMemoryBarrierCount, pImageMemoryBarriers); -}