X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fintel%2Fvulkan%2FgenX_gpu_memcpy.c;h=57dc55ec39415902037d389e710b60c3616934a5;hb=512db7ec78a9d334e561ef0f6a3ae68aa10a6824;hp=11ffd6fb436f167b6857b805379a0a1e3c01684e;hpb=40149441b8e2c9b806fc0f6a387a7653d97a3b59;p=mesa.git diff --git a/src/intel/vulkan/genX_gpu_memcpy.c b/src/intel/vulkan/genX_gpu_memcpy.c index 11ffd6fb436..57dc55ec394 100644 --- a/src/intel/vulkan/genX_gpu_memcpy.c +++ b/src/intel/vulkan/genX_gpu_memcpy.c @@ -51,80 +51,6 @@ gcd_pow2_u64(uint64_t a, uint64_t b) return 1 << MIN2(a_log2, b_log2); } -void -genX(cmd_buffer_mi_memcpy)(struct anv_cmd_buffer *cmd_buffer, - struct anv_address dst, struct anv_address src, - uint32_t size) -{ - /* This memcpy operates in units of dwords. */ - assert(size % 4 == 0); - assert(dst.offset % 4 == 0); - assert(src.offset % 4 == 0); - -#if GEN_GEN == 7 - /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM - * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is - * in-flight when they are issued even if the memory touched is not - * currently active for rendering. The weird bit is that it is not the - * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight - * rendering hangs such that the next stalling command after the - * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang. - * - * It is unclear exactly why this hang occurs. Both MI commands come with - * warnings about the 3D pipeline but that doesn't seem to fully explain - * it. My (Jason's) best theory is that it has something to do with the - * fact that we're using a GPU state register as our temporary and that - * something with reading/writing it is causing problems. - * - * In order to work around this issue, we emit a PIPE_CONTROL with the - * command streamer stall bit set. - */ - cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT; - genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer); -#endif - - for (uint32_t i = 0; i < size; i += 4) { -#if GEN_GEN >= 8 - anv_batch_emit(&cmd_buffer->batch, GENX(MI_COPY_MEM_MEM), cp) { - cp.DestinationMemoryAddress = anv_address_add(dst, i); - cp.SourceMemoryAddress = anv_address_add(src, i); - } -#else - /* IVB does not have a general purpose register for command streamer - * commands. Therefore, we use an alternate temporary register. - */ -#define TEMP_REG 0x2440 /* GEN7_3DPRIM_BASE_VERTEX */ - anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_MEM), load) { - load.RegisterAddress = TEMP_REG; - load.MemoryAddress = anv_address_add(src, i); - } - anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), store) { - store.RegisterAddress = TEMP_REG; - store.MemoryAddress = anv_address_add(dst, i); - } -#undef TEMP_REG -#endif - } - return; -} - -void -genX(cmd_buffer_mi_memset)(struct anv_cmd_buffer *cmd_buffer, - struct anv_address dst, uint32_t value, - uint32_t size) -{ - /* This memset operates in units of dwords. */ - assert(size % 4 == 0); - assert(dst.offset % 4 == 0); - - for (uint32_t i = 0; i < size; i += 4) { - anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) { - sdi.Address = anv_address_add(dst, i); - sdi.ImmediateData = value; - } - } -} - void genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, struct anv_address dst, struct anv_address src, @@ -133,14 +59,9 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, if (size == 0) return; - assert(dst.offset + size <= dst.bo->size); - assert(src.offset + size <= src.bo->size); - /* The maximum copy block size is 4 32-bit components at a time. */ - unsigned bs = 16; - bs = gcd_pow2_u64(bs, src.offset); - bs = gcd_pow2_u64(bs, dst.offset); - bs = gcd_pow2_u64(bs, size); + assert(size % 4 == 0); + unsigned bs = gcd_pow2_u64(16, size); enum isl_format format; switch (bs) { @@ -157,6 +78,7 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, genX(cmd_buffer_config_l3)(cmd_buffer, cfg); } + genX(cmd_buffer_set_binding_for_gen8_vb_flush)(cmd_buffer, 32, src, size); genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer); genX(flush_pipeline_select_3d)(cmd_buffer); @@ -169,11 +91,10 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, .AddressModifyEnable = true, .BufferStartingAddress = src, .BufferPitch = bs, + .MOCS = anv_mocs_for_bo(cmd_buffer->device, src.bo), #if (GEN_GEN >= 8) - .MemoryObjectControlState = GENX(MOCS), .BufferSize = size, #else - .VertexBufferMemoryObjectControlState = GENX(MOCS), .EndAddress = anv_address_add(src, size - 1), #endif }); @@ -191,6 +112,13 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, .Component3Control = (bs >= 16) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0, }); +#if GEN_GEN >= 8 + anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_INSTANCING), vfi) { + vfi.InstancingEnable = false; + vfi.VertexElementIndex = 0; + } +#endif + #if GEN_GEN >= 8 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_SGVS), sgvs); #endif @@ -226,11 +154,16 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, genX(emit_urb_setup)(cmd_buffer->device, &cmd_buffer->batch, cmd_buffer->state.current_l3_config, - VK_SHADER_STAGE_VERTEX_BIT, entry_size); + VK_SHADER_STAGE_VERTEX_BIT, entry_size, NULL); anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_SO_BUFFER), sob) { +#if GEN_GEN < 12 sob.SOBufferIndex = 0; - sob.SOBufferObjectControlState = GENX(MOCS); +#else + sob._3DCommandOpcode = 0; + sob._3DCommandSubOpcode = SO_BUFFER_INDEX_0_CMD; +#endif + sob.MOCS = anv_mocs_for_bo(cmd_buffer->device, dst.bo), sob.SurfaceBaseAddress = dst; #if GEN_GEN >= 8 @@ -294,6 +227,11 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, vf.StatisticsEnable = false; } +#if GEN_GEN >= 12 + /* Disable Primitive Replication. */ + anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_PRIMITIVE_REPLICATION), pr); +#endif + anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) { prim.VertexAccessType = SEQUENTIAL; prim.PrimitiveTopologyType = _3DPRIM_POINTLIST; @@ -304,5 +242,8 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, prim.BaseVertexLocation = 0; } + genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush)(cmd_buffer, SEQUENTIAL, + 1ull << 32); + cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE; }