X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fintel%2Fvulkan%2FgenX_state.c;h=84c43473774cfa64227f055270e8b6a900bf76c1;hb=aad0e6f81049c098fd3922d61aa228e4bf791317;hp=fd8f8ac9ce03937415ab46f0473d2352a1193d3f;hpb=de05ecba9f980547a4638e8d235d64ecf83d79e0;p=mesa.git diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index fd8f8ac9ce0..84c43473774 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -29,16 +29,89 @@ #include "anv_private.h" +#include "common/gen_aux_map.h" #include "common/gen_sample_positions.h" #include "genxml/gen_macros.h" #include "genxml/genX_pack.h" +#include "vk_util.h" + +static void +genX(emit_slice_hashing_state)(struct anv_device *device, + struct anv_batch *batch) +{ + device->slice_hash = (struct anv_state) { 0 }; + +#if GEN_GEN == 11 + const unsigned *ppipe_subslices = device->info.ppipe_subslices; + int subslices_delta = ppipe_subslices[0] - ppipe_subslices[1]; + if (subslices_delta == 0) + return; + + unsigned size = GENX(SLICE_HASH_TABLE_length) * 4; + device->slice_hash = + anv_state_pool_alloc(&device->dynamic_state_pool, size, 64); + + struct GENX(SLICE_HASH_TABLE) table0 = { + .Entry = { + { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 }, + { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 }, + { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 }, + { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 }, + { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 }, + { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 }, + { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 }, + { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 }, + { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 }, + { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 }, + { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 }, + { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 }, + { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 }, + { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 }, + { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 }, + { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 } + } + }; + + struct GENX(SLICE_HASH_TABLE) table1 = { + .Entry = { + { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 }, + { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 }, + { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 }, + { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 }, + { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 }, + { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 }, + { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 }, + { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 }, + { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 }, + { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 }, + { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 }, + { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 }, + { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 }, + { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 }, + { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 }, + { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 } + } + }; + + const struct GENX(SLICE_HASH_TABLE) *table = + subslices_delta < 0 ? &table0 : &table1; + GENX(SLICE_HASH_TABLE_pack)(NULL, device->slice_hash.map, table); + + anv_batch_emit(batch, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS), ptr) { + ptr.SliceHashStatePointerValid = true; + ptr.SliceHashTableStatePointer = device->slice_hash.offset; + } + + anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) { + mode.SliceHashingTableEnable = true; + } +#endif +} + VkResult genX(init_device_state)(struct anv_device *device) { - GENX(MEMORY_OBJECT_CONTROL_STATE_pack)(NULL, &device->default_mocs, - &GENX(MOCS)); - struct anv_batch batch; uint32_t cmds[64]; @@ -52,8 +125,19 @@ genX(init_device_state)(struct anv_device *device) ps.PipelineSelection = _3D; } - anv_batch_emit(&batch, GENX(3DSTATE_VF_STATISTICS), vfs) - vfs.StatisticsEnable = true; +#if GEN_GEN == 9 + uint32_t cache_mode_1; + anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1), + .FloatBlendOptimizationEnable = true, + .FloatBlendOptimizationEnableMask = true, + .PartialResolveDisableInVC = true, + .PartialResolveDisableInVCMask = true); + + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(CACHE_MODE_1_num); + lri.DataDWord = cache_mode_1; + } +#endif anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa); @@ -81,16 +165,127 @@ genX(init_device_state)(struct anv_device *device) GEN_SAMPLE_POS_16X(sp._16xSample); #endif } + + /* The BDW+ docs describe how to use the 3DSTATE_WM_HZ_OP instruction in the + * section titled, "Optimized Depth Buffer Clear and/or Stencil Buffer + * Clear." It mentions that the packet overrides GPU state for the clear + * operation and needs to be reset to 0s to clear the overrides. Depending + * on the kernel, we may not get a context with the state for this packet + * zeroed. Do it ourselves just in case. We've observed this to prevent a + * number of GPU hangs on ICL. + */ + anv_batch_emit(&batch, GENX(3DSTATE_WM_HZ_OP), hzp); +#endif + +#if GEN_GEN == 11 + /* The default behavior of bit 5 "Headerless Message for Pre-emptable + * Contexts" in SAMPLER MODE register is set to 0, which means + * headerless sampler messages are not allowed for pre-emptable + * contexts. Set the bit 5 to 1 to allow them. + */ + uint32_t sampler_mode; + anv_pack_struct(&sampler_mode, GENX(SAMPLER_MODE), + .HeaderlessMessageforPreemptableContexts = true, + .HeaderlessMessageforPreemptableContextsMask = true); + + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(SAMPLER_MODE_num); + lri.DataDWord = sampler_mode; + } + + /* Bit 1 "Enabled Texel Offset Precision Fix" must be set in + * HALF_SLICE_CHICKEN7 register. + */ + uint32_t half_slice_chicken7; + anv_pack_struct(&half_slice_chicken7, GENX(HALF_SLICE_CHICKEN7), + .EnabledTexelOffsetPrecisionFix = true, + .EnabledTexelOffsetPrecisionFixMask = true); + + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(HALF_SLICE_CHICKEN7_num); + lri.DataDWord = half_slice_chicken7; + } + + uint32_t tccntlreg; + anv_pack_struct(&tccntlreg, GENX(TCCNTLREG), + .L3DataPartialWriteMergingEnable = true, + .ColorZPartialWriteMergingEnable = true, + .URBPartialWriteMergingEnable = true, + .TCDisable = true); + + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(TCCNTLREG_num); + lri.DataDWord = tccntlreg; + } + +#endif + genX(emit_slice_hashing_state)(device, &batch); + +#if GEN_GEN >= 11 + /* hardware specification recommends disabling repacking for + * the compatibility with decompression mechanism in display controller. + */ + if (device->info.disable_ccs_repack) { + uint32_t cache_mode_0; + anv_pack_struct(&cache_mode_0, + GENX(CACHE_MODE_0), + .DisableRepackingforCompression = true, + .DisableRepackingforCompressionMask = true); + + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(CACHE_MODE_0_num); + lri.DataDWord = cache_mode_0; + } + } +#endif + +#if GEN_GEN == 12 + uint64_t aux_base_addr = gen_aux_map_get_base(device->aux_map_ctx); + assert(aux_base_addr % (32 * 1024) == 0); + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num); + lri.DataDWord = aux_base_addr & 0xffffffff; + } + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num) + 4; + lri.DataDWord = aux_base_addr >> 32; + } +#endif + + /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so + * 3DSTATE_CONSTANT_XS buffer 0 is an absolute address. + * + * This is only safe on kernels with context isolation support. + */ + if (GEN_GEN >= 8 && device->physical->has_context_isolation) { + UNUSED uint32_t tmp_reg; +#if GEN_GEN >= 9 + anv_pack_struct(&tmp_reg, GENX(CS_DEBUG_MODE2), + .CONSTANT_BUFFERAddressOffsetDisable = true, + .CONSTANT_BUFFERAddressOffsetDisableMask = true); + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(CS_DEBUG_MODE2_num); + lri.DataDWord = tmp_reg; + } +#elif GEN_GEN == 8 + anv_pack_struct(&tmp_reg, GENX(INSTPM), + .CONSTANT_BUFFERAddressOffsetDisable = true, + .CONSTANT_BUFFERAddressOffsetDisableMask = true); + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(INSTPM_num); + lri.DataDWord = tmp_reg; + } #endif + } anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe); assert(batch.next <= batch.end); - return anv_device_submit_simple_batch(device, &batch); + return anv_queue_submit_simple_batch(&device->queue, &batch); } -static inline uint32_t +static uint32_t vk_to_gen_tex_filter(VkFilter filter, bool anisotropyEnable) { switch (filter) { @@ -103,7 +298,7 @@ vk_to_gen_tex_filter(VkFilter filter, bool anisotropyEnable) } } -static inline uint32_t +static uint32_t vk_to_gen_max_anisotropy(float ratio) { return (anv_clamp_f(ratio, 2, 16) - 2) / 2; @@ -144,6 +339,14 @@ static const uint32_t vk_to_gen_shadow_compare_op[] = { [VK_COMPARE_OP_ALWAYS] = PREFILTEROPNEVER, }; +#if GEN_GEN >= 9 +static const uint32_t vk_to_gen_sampler_reduction_mode[] = { + [VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT] = STD_FILTER, + [VK_SAMPLER_REDUCTION_MODE_MIN_EXT] = MINIMUM, + [VK_SAMPLER_REDUCTION_MODE_MAX_EXT] = MAXIMUM, +}; +#endif + VkResult genX(CreateSampler)( VkDevice _device, const VkSamplerCreateInfo* pCreateInfo, @@ -155,68 +358,148 @@ VkResult genX(CreateSampler)( assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO); - sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8, + sampler = vk_zalloc2(&device->alloc, pAllocator, sizeof(*sampler), 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); if (!sampler) return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY); + sampler->n_planes = 1; + + uint32_t border_color_stride = GEN_IS_HASWELL ? 512 : 64; uint32_t border_color_offset = device->border_colors.offset + - pCreateInfo->borderColor * 64; + pCreateInfo->borderColor * + border_color_stride; + +#if GEN_GEN >= 9 + unsigned sampler_reduction_mode = STD_FILTER; + bool enable_sampler_reduction = false; +#endif + + vk_foreach_struct(ext, pCreateInfo->pNext) { + switch (ext->sType) { + case VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_INFO: { + VkSamplerYcbcrConversionInfo *pSamplerConversion = + (VkSamplerYcbcrConversionInfo *) ext; + ANV_FROM_HANDLE(anv_ycbcr_conversion, conversion, + pSamplerConversion->conversion); + + /* Ignore conversion for non-YUV formats. This fulfills a requirement + * for clients that want to utilize same code path for images with + * external formats (VK_FORMAT_UNDEFINED) and "regular" RGBA images + * where format is known. + */ + if (conversion == NULL || !conversion->format->can_ycbcr) + break; + + sampler->n_planes = conversion->format->n_planes; + sampler->conversion = conversion; + break; + } +#if GEN_GEN >= 9 + case VK_STRUCTURE_TYPE_SAMPLER_REDUCTION_MODE_CREATE_INFO: { + VkSamplerReductionModeCreateInfo *sampler_reduction = + (VkSamplerReductionModeCreateInfo *) ext; + sampler_reduction_mode = + vk_to_gen_sampler_reduction_mode[sampler_reduction->reductionMode]; + enable_sampler_reduction = true; + break; + } +#endif + default: + anv_debug_ignored_stype(ext->sType); + break; + } + } - bool enable_min_filter_addr_rounding = - pCreateInfo->minFilter != VK_FILTER_NEAREST; - bool enable_mag_filter_addr_rounding = - pCreateInfo->magFilter != VK_FILTER_NEAREST; + if (device->physical->has_bindless_samplers) { + /* If we have bindless, allocate enough samplers. We allocate 32 bytes + * for each sampler instead of 16 bytes because we want all bindless + * samplers to be 32-byte aligned so we don't have to use indirect + * sampler messages on them. + */ + sampler->bindless_state = + anv_state_pool_alloc(&device->dynamic_state_pool, + sampler->n_planes * 32, 32); + } - struct GENX(SAMPLER_STATE) sampler_state = { - .SamplerDisable = false, - .TextureBorderColorMode = DX10OGL, + for (unsigned p = 0; p < sampler->n_planes; p++) { + const bool plane_has_chroma = + sampler->conversion && sampler->conversion->format->planes[p].has_chroma; + const VkFilter min_filter = + plane_has_chroma ? sampler->conversion->chroma_filter : pCreateInfo->minFilter; + const VkFilter mag_filter = + plane_has_chroma ? sampler->conversion->chroma_filter : pCreateInfo->magFilter; + const bool enable_min_filter_addr_rounding = min_filter != VK_FILTER_NEAREST; + const bool enable_mag_filter_addr_rounding = mag_filter != VK_FILTER_NEAREST; + /* From Broadwell PRM, SAMPLER_STATE: + * "Mip Mode Filter must be set to MIPFILTER_NONE for Planar YUV surfaces." + */ + const uint32_t mip_filter_mode = + (sampler->conversion && + isl_format_is_yuv(sampler->conversion->format->planes[0].isl_format)) ? + MIPFILTER_NONE : vk_to_gen_mipmap_mode[pCreateInfo->mipmapMode]; + + struct GENX(SAMPLER_STATE) sampler_state = { + .SamplerDisable = false, + .TextureBorderColorMode = DX10OGL, #if GEN_GEN >= 8 - .LODPreClampMode = CLAMP_MODE_OGL, + .LODPreClampMode = CLAMP_MODE_OGL, #else - .LODPreClampEnable = CLAMP_ENABLE_OGL, + .LODPreClampEnable = CLAMP_ENABLE_OGL, #endif #if GEN_GEN == 8 - .BaseMipLevel = 0.0, -#endif - .MipModeFilter = vk_to_gen_mipmap_mode[pCreateInfo->mipmapMode], - .MagModeFilter = vk_to_gen_tex_filter(pCreateInfo->magFilter, - pCreateInfo->anisotropyEnable), - .MinModeFilter = vk_to_gen_tex_filter(pCreateInfo->minFilter, - pCreateInfo->anisotropyEnable), - .TextureLODBias = anv_clamp_f(pCreateInfo->mipLodBias, -16, 15.996), - .AnisotropicAlgorithm = EWAApproximation, - .MinLOD = anv_clamp_f(pCreateInfo->minLod, 0, 14), - .MaxLOD = anv_clamp_f(pCreateInfo->maxLod, 0, 14), - .ChromaKeyEnable = 0, - .ChromaKeyIndex = 0, - .ChromaKeyMode = 0, - .ShadowFunction = vk_to_gen_shadow_compare_op[pCreateInfo->compareOp], - .CubeSurfaceControlMode = OVERRIDE, - - .BorderColorPointer = border_color_offset, + .BaseMipLevel = 0.0, +#endif + .MipModeFilter = mip_filter_mode, + .MagModeFilter = vk_to_gen_tex_filter(mag_filter, pCreateInfo->anisotropyEnable), + .MinModeFilter = vk_to_gen_tex_filter(min_filter, pCreateInfo->anisotropyEnable), + .TextureLODBias = anv_clamp_f(pCreateInfo->mipLodBias, -16, 15.996), + .AnisotropicAlgorithm = + pCreateInfo->anisotropyEnable ? EWAApproximation : LEGACY, + .MinLOD = anv_clamp_f(pCreateInfo->minLod, 0, 14), + .MaxLOD = anv_clamp_f(pCreateInfo->maxLod, 0, 14), + .ChromaKeyEnable = 0, + .ChromaKeyIndex = 0, + .ChromaKeyMode = 0, + .ShadowFunction = + vk_to_gen_shadow_compare_op[pCreateInfo->compareEnable ? + pCreateInfo->compareOp : VK_COMPARE_OP_NEVER], + .CubeSurfaceControlMode = OVERRIDE, + + .BorderColorPointer = border_color_offset, #if GEN_GEN >= 8 - .LODClampMagnificationMode = MIPNONE, -#endif - - .MaximumAnisotropy = vk_to_gen_max_anisotropy(pCreateInfo->maxAnisotropy), - .RAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding, - .RAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding, - .VAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding, - .VAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding, - .UAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding, - .UAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding, - .TrilinearFilterQuality = 0, - .NonnormalizedCoordinateEnable = pCreateInfo->unnormalizedCoordinates, - .TCXAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeU], - .TCYAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeV], - .TCZAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeW], - }; + .LODClampMagnificationMode = MIPNONE, +#endif + + .MaximumAnisotropy = vk_to_gen_max_anisotropy(pCreateInfo->maxAnisotropy), + .RAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding, + .RAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding, + .VAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding, + .VAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding, + .UAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding, + .UAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding, + .TrilinearFilterQuality = 0, + .NonnormalizedCoordinateEnable = pCreateInfo->unnormalizedCoordinates, + .TCXAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeU], + .TCYAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeV], + .TCZAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeW], + +#if GEN_GEN >= 9 + .ReductionType = sampler_reduction_mode, + .ReductionTypeEnable = enable_sampler_reduction, +#endif + }; - GENX(SAMPLER_STATE_pack)(NULL, sampler->state, &sampler_state); + GENX(SAMPLER_STATE_pack)(NULL, sampler->state[p], &sampler_state); + + if (sampler->bindless_state.map) { + memcpy(sampler->bindless_state.map + p * 32, + sampler->state[p], GENX(SAMPLER_STATE_length) * 4); + } + } *pSampler = anv_sampler_to_handle(sampler);