X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fls2.py;h=3aa51e48d9d3f017e707303961ec666b7527e9bd;hb=9b5409183b6f4171852dcc112975211877d7bda9;hp=e4a7188489e2337870331ecf4fa5ec811f65d926;hpb=31ded07abc024811c48fd0b7b2378841065ac2bf;p=ls2.git

diff --git a/src/ls2.py b/src/ls2.py
index e4a7188..3aa51e4 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -51,7 +51,7 @@ from nmigen_boards.arty_a7 import ArtyA7_100Platform
 from nmigen_boards.test.blinky import Blinky
 from icarusversa import IcarusVersaPlatform
 # Clock-Reset Generator (works for all ECP5 platforms)
-from crg import ECPIX5CRG
+from ecp5_crg import ECP5CRG
 from arty_crg import ArtyA7CRG
 
 import sys
@@ -272,7 +272,7 @@ class DDR3SoC(SoC, Elaboratable):
 
         # set up clock request generator
         if fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim', 'ulx3s']:
-            self.crg = ECPIX5CRG(clk_freq)
+            self.crg = ECP5CRG(clk_freq)
         if fpga in ['arty_a7']:
             self.crg = ArtyA7CRG(clk_freq)
 
@@ -578,10 +578,14 @@ def build_platform(fpga, firmware):
     else:
         platform = None
 
+    print ("platform", fpga, firmware, platform)
+
     # set clock frequency
     clk_freq = 70e6
     if fpga == 'sim':
         clk_freq = 100e6
+    if fpga == 'isim':
+        clk_freq = 50e6 # below 50 mhz, stops DRAM being enabled
     if fpga == 'versa_ecp5':
         clk_freq = 50e6 # crank right down to test hyperram
     if fpga == 'versa_ecp5_85':
@@ -589,7 +593,7 @@ def build_platform(fpga, firmware):
     if fpga == 'arty_a7':
         clk_freq = 50e6
     if fpga == 'ulx3s':
-        clk_freq = 12.5e6
+        clk_freq = 40.0e6
 
     # select a firmware address
     fw_addr = None
@@ -631,8 +635,17 @@ def build_platform(fpga, firmware):
 
     # Get HyperRAM pins
     hyperram_pins = None
-    if platform is None or platform in ['isim']:
+    if platform is None:
         hyperram_pins = HyperRAMPads()
+    elif fpga in ['isim']:
+        hyperram_ios = HyperRAMResource(0, cs_n="B11",
+                                        dq="D4 D3 F4 F3 G2 H2 D2 E2",
+                                        rwds="U13", rst_n="T13", ck_p="V10",
+                                        # ck_n="D12" - for later (DDR)
+                                        attrs=Attrs(IOSTANDARD="LVCMOS33"))
+        platform.add_resources(hyperram_ios)
+        hyperram_pins = platform.request("hyperram")
+        print ("isim a7 hyperram", hyperram_ios)
     # Digilent Arty A7-100t
     elif platform is not None and fpga in ['arty_a7']:
         hyperram_ios = HyperRAMResource(0, cs_n="B11",
@@ -652,6 +665,7 @@ def build_platform(fpga, firmware):
         platform.add_resources(hyperram_ios)
         hyperram_pins = platform.request("hyperram")
         print ("versa ecp5 hyperram", hyperram_ios)
+    print ("hyperram pins", hyperram_pins)
 
     # set up the SOC
     soc = DDR3SoC(fpga=fpga, dram_cls=dram_cls,