X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fgpio%2FGPIOPeriphery.scala;fp=src%2Fmain%2Fscala%2Fdevices%2Fgpio%2FGPIOPeriphery.scala;h=38fd20ad8bdd2ee6bc7781fe1b8bc5afb4470ec4;hb=27b00e177c2b4cd29234e556b3b6a0260d151431;hp=20f8b5d8172438746251a471dd1f205d346ef78a;hpb=0ca609d324424dc2488e51273ec89c5714d3c95e;p=sifive-blocks.git

diff --git a/src/main/scala/devices/gpio/GPIOPeriphery.scala b/src/main/scala/devices/gpio/GPIOPeriphery.scala
index 20f8b5d..38fd20a 100644
--- a/src/main/scala/devices/gpio/GPIOPeriphery.scala
+++ b/src/main/scala/devices/gpio/GPIOPeriphery.scala
@@ -10,23 +10,29 @@ import rocketchip.{
   HasTopLevelNetworksModule
 }
 import uncore.tilelink2.TLFragmenter
+import util.HeterogeneousBag
 
-case object PeripheryGPIOKey extends Field[GPIOParams]
+case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
 
 trait HasPeripheryGPIO extends HasTopLevelNetworks {
   val gpioParams = p(PeripheryGPIOKey)
-  val gpio = LazyModule(new TLGPIO(peripheryBusBytes, gpioParams))
-  gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-  intBus.intnode := gpio.intnode
+  val gpio = gpioParams map {params =>
+    val gpio = LazyModule(new TLGPIO(peripheryBusBytes, params))
+    gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
+    intBus.intnode := gpio.intnode
+    gpio
+  }
 }
 
 trait HasPeripheryGPIOBundle extends HasTopLevelNetworksBundle {
   val outer: HasPeripheryGPIO
-  val gpio = new GPIOPortIO(outer.gpioParams)
+  val gpio = HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_)))
 }
 
 trait HasPeripheryGPIOModule extends HasTopLevelNetworksModule {
   val outer: HasPeripheryGPIO
   val io: HasPeripheryGPIOBundle
-  io.gpio <> outer.gpio.module.io.port
+  (io.gpio zip outer.gpio) foreach { case (io, device) =>
+    io <> device.module.io.port
+  }
 }