X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fgpio%2FGPIOPins.scala;fp=src%2Fmain%2Fscala%2Fdevices%2Fgpio%2FGPIOPins.scala;h=de086bf9f5dbd94d83fbc672c26d1c33ad2ae082;hb=86010395adffd9ee4a42f5240b08bb0f243972ff;hp=0000000000000000000000000000000000000000;hpb=5e51e1e93172b5c5b6c436196f8dad68678eb93d;p=sifive-blocks.git

diff --git a/src/main/scala/devices/gpio/GPIOPins.scala b/src/main/scala/devices/gpio/GPIOPins.scala
new file mode 100644
index 0000000..de086bf
--- /dev/null
+++ b/src/main/scala/devices/gpio/GPIOPins.scala
@@ -0,0 +1,27 @@
+// See LICENSE for license details.
+package sifive.blocks.devices.gpio
+
+import Chisel._
+import sifive.blocks.devices.pinctrl.{Pin}
+
+// While this is a bit pendantic, it keeps the GPIO
+// device more similar to the other devices. It's not 'special'
+// even though it looks like something that more directly talks to
+// a pin. It also makes it possible to change the exact
+// type of pad this connects to.
+class GPIOPins[T <: Pin] (pingen: ()=> T,  c: GPIOParams) extends Bundle {
+
+  val pins = Vec(c.width, pingen())
+
+  override def cloneType: this.type =
+    this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
+
+  def fromPort(port: GPIOPortIO){
+
+    // This will just match up the components of the Bundle that
+    // exist in both.
+    (pins zip port.pins) foreach {case (pin, port) =>
+      pin <> port
+    }
+  }
+}