X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fi2c%2FI2C.scala;fp=src%2Fmain%2Fscala%2Fdevices%2Fi2c%2FI2C.scala;h=58ad5482688f8f193e8f047ba4cd1d0202675444;hb=4ab5cb022bea37b81b20ff92280bf97658a98467;hp=f0df22a6e48702d5f2e845962df229949390a078;hpb=66b2fd11bd1ec6a8a05c4929893c51c7570284fd;p=sifive-blocks.git

diff --git a/src/main/scala/devices/i2c/I2C.scala b/src/main/scala/devices/i2c/I2C.scala
index f0df22a..58ad548 100644
--- a/src/main/scala/devices/i2c/I2C.scala
+++ b/src/main/scala/devices/i2c/I2C.scala
@@ -42,10 +42,10 @@
 package sifive.blocks.devices.i2c
 
 import Chisel._
-import config._
-import regmapper._
-import uncore.tilelink2._
-import util.{AsyncResetRegVec, Majority}
+import freechips.rocketchip.config._
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util.{AsyncResetRegVec, Majority}
 import sifive.blocks.devices.gpio.{GPIOPinCtrl}
 
 case class I2CParams(address: BigInt)