X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fspi%2FSPIPeriphery.scala;fp=src%2Fmain%2Fscala%2Fdevices%2Fspi%2FSPIPeriphery.scala;h=f4773a228c7cabf9646381ed4b9cea756be77270;hb=c010a1557aba5e1f9dc004c1ad9ec2cb26eabcfd;hp=40bcec692f9265f5b9fa590a09a060194244ff23;hpb=535be3e9761218a864bb553d996296dc65ea1735;p=sifive-blocks.git

diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala
index 40bcec6..f4773a2 100644
--- a/src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/src/main/scala/devices/spi/SPIPeriphery.scala
@@ -8,8 +8,8 @@ import rocketchip.{TopNetwork,TopNetworkModule}
 
 trait PeripherySPI {
   this: TopNetwork { val spiConfigs: Seq[SPIConfig] } =>
-  val spiDevices = (spiConfigs.zipWithIndex) map {case (c, i) =>
-    val spi = LazyModule(new TLSPI(c) { override lazy val valName = Some(s"spi$i") } )
+  val spi = (spiConfigs.zipWithIndex) map {case (c, i) =>
+    val spi = LazyModule(new TLSPI(c))
     spi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
     intBus.intnode := spi.intnode
     spi
@@ -28,7 +28,7 @@ trait PeripherySPIModule {
     val outer: PeripherySPI
     val io: PeripherySPIBundle
   } =>
-  (io.spis zip outer.spiDevices).foreach { case (io, device) =>
+  (io.spis zip outer.spi).foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }