X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fspi%2FTLSPI.scala;fp=src%2Fmain%2Fscala%2Fdevices%2Fspi%2FTLSPI.scala;h=0af8e35150ba077fc573f33074f39a699e0fcd5a;hb=4ab5cb022bea37b81b20ff92280bf97658a98467;hp=5c5b9bfe5409fd91a1bd411e16d5cbc420a14283;hpb=66b2fd11bd1ec6a8a05c4929893c51c7570284fd;p=sifive-blocks.git

diff --git a/src/main/scala/devices/spi/TLSPI.scala b/src/main/scala/devices/spi/TLSPI.scala
index 5c5b9bf..0af8e35 100644
--- a/src/main/scala/devices/spi/TLSPI.scala
+++ b/src/main/scala/devices/spi/TLSPI.scala
@@ -2,11 +2,11 @@
 package sifive.blocks.devices.spi
 
 import Chisel._
-import config._
-import diplomacy._
-import regmapper._
-import uncore.tilelink2._
-
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util.HeterogeneousBag
 import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}
 
 trait SPIParamsBase {
@@ -47,7 +47,7 @@ case class SPIParams(
   require(sampleDelay >= 0)
 }
 
-class SPITopBundle(val i: util.HeterogeneousBag[Vec[Bool]], val r: util.HeterogeneousBag[TLBundle]) extends Bundle
+class SPITopBundle(val i: HeterogeneousBag[Vec[Bool]], val r: HeterogeneousBag[TLBundle]) extends Bundle
 
 class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLSPIBase)
   extends LazyModuleImp(outer) {