X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fuart%2FUARTPins.scala;h=88fa34c781860f0154e9982035efa4f2b10089b4;hb=39287b92159e7f7a25635dfe7cc5cb7dc01488bc;hp=4201f90d7b164ec2442224452116041b7920d8b0;hpb=4fcf349adb9e66ea7d8cc5394de5d3e0a2340985;p=sifive-blocks.git

diff --git a/src/main/scala/devices/uart/UARTPins.scala b/src/main/scala/devices/uart/UARTPins.scala
index 4201f90..88fa34c 100644
--- a/src/main/scala/devices/uart/UARTPins.scala
+++ b/src/main/scala/devices/uart/UARTPins.scala
@@ -3,21 +3,15 @@ package sifive.blocks.devices.uart
 
 import Chisel._
 import chisel3.experimental.{withClockAndReset}
-import freechips.rocketchip.config.Field
 import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
-import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus}
-import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import sifive.blocks.devices.pinctrl.{Pin}
 
-class UARTSignals[T <: Data] (pingen: () => T) extends Bundle {
+class UARTSignals[T <: Data](private val pingen: () => T) extends Bundle {
   val rxd = pingen()
   val txd = pingen()
-
-  override def cloneType: this.type =
-    this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
 }
 
-class UARTPins[T <: Pin] (pingen: () => T) extends UARTSignals[T](pingen)
+class UARTPins[T <: Pin](pingen: () => T) extends UARTSignals[T](pingen)
 
 object UARTPinsFromPort {
   def apply[T <: Pin](pins: UARTSignals[T], uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {