X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fxilinxvc707mig%2FXilinxVC707MIG.scala;fp=src%2Fmain%2Fscala%2Fdevices%2Fxilinxvc707mig%2FXilinxVC707MIG.scala;h=931e9befecc29f25aac4f602292579e0ea1fb684;hb=3d8c502fce3f4920b226026c07fd47325af5fba1;hp=f6ae153107a4ff9558056f54c3703004baab7643;hpb=2154e9eb3f2357cdbe005836c710012c3e8e4b1c;p=sifive-blocks.git

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
index f6ae153..931e9be 100644
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
@@ -24,7 +24,7 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
   val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
     slaves = Seq(AXI4SlaveParameters(
       address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)),
-      resources     = device.reg,
+      resources     = device.reg("mem"),
       regionType    = RegionType.UNCACHED,
       executable    = true,
       supportsWrite = TransferSizes(1, 256*8),