X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fip%2Fxilinx%2Fvc707axi_to_pcie_x1%2Fvc707axi_to_pcie_x1.scala;fp=src%2Fmain%2Fscala%2Fip%2Fxilinx%2Fvc707axi_to_pcie_x1%2Fvc707axi_to_pcie_x1.scala;h=ac9745f46672dc61b9a970021fa7ab4e6d77b8bc;hb=0ca609d324424dc2488e51273ec89c5714d3c95e;hp=fa4b31bc2da199d7e22883237fd2fc00fb16e7c5;hpb=0f8722f80c16a649882d02f03d000da946eee737;p=sifive-blocks.git

diff --git a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
index fa4b31b..ac9745f 100644
--- a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
+++ b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
@@ -181,7 +181,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
         "device_type"        -> Seq(ResourceString("pci")),
         "interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt),
         "interrupt-map"      -> Seq(1, 2, 3, 4).flatMap(ofMap),
-        "ranges"             -> resources("ranges").map { case Binding(_, ResourceAddress(address, _, _, _)) =>
+        "ranges"             -> resources("ranges").map { case Binding(_, ResourceAddress(address, _, _, _, _)) =>
                                                                ResourceMapping(address, BigInt(0x02000000) << 64) },
         "interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map(
           "interrupt-controller" -> Nil,
@@ -211,6 +211,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
 
   val master = AXI4MasterNode(Seq(AXI4MasterPortParameters(
     masters = Seq(AXI4MasterParameters(
+      name    = "VC707 PCIe",
       id      = IdRange(0, 1),
       aligned = false)))))