X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fip%2Fxilinx%2Fvc707axi_to_pcie_x1%2Fvc707axi_to_pcie_x1.scala;fp=src%2Fmain%2Fscala%2Fip%2Fxilinx%2Fvc707axi_to_pcie_x1%2Fvc707axi_to_pcie_x1.scala;h=c7206e41e78666c8fa98c2f533cf85081ba0527e;hb=3d8c502fce3f4920b226026c07fd47325af5fba1;hp=ac9745f46672dc61b9a970021fa7ab4e6d77b8bc;hpb=2154e9eb3f2357cdbe005836c710012c3e8e4b1c;p=sifive-blocks.git

diff --git a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
index ac9745f..c7206e4 100644
--- a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
+++ b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
@@ -181,8 +181,8 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
         "device_type"        -> Seq(ResourceString("pci")),
         "interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt),
         "interrupt-map"      -> Seq(1, 2, 3, 4).flatMap(ofMap),
-        "ranges"             -> resources("ranges").map { case Binding(_, ResourceAddress(address, _, _, _, _)) =>
-                                                               ResourceMapping(address, BigInt(0x02000000) << 64) },
+        "ranges"             -> resources("ranges").map { case Binding(_, ResourceAddress(address, perms)) =>
+                                                               ResourceMapping(address, BigInt(0x02000000) << 64, perms) },
         "interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map(
           "interrupt-controller" -> Nil,
           "#address-cells"       -> ofInt(0),
@@ -203,7 +203,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
   val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
     slaves = Seq(AXI4SlaveParameters(
       address       = List(AddressSet(0x50000000L, 0x03ffffffL)),
-      resources     = device.reg,
+      resources     = device.reg("control"),
       supportsWrite = TransferSizes(1, 4),
       supportsRead  = TransferSizes(1, 4),
       interleavedId = Some(0))), // AXI4-Lite never interleaves responses