X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fip%2Fxilinx%2Fvc707mig%2Fvc707mig.scala;fp=src%2Fmain%2Fscala%2Fip%2Fxilinx%2Fvc707mig%2Fvc707mig.scala;h=1e01748b531eac309e5f3087149ca1fee2619587;hb=4ab5cb022bea37b81b20ff92280bf97658a98467;hp=d7b522fd7eaa0ab38c7a67638387353fe60ddeb5;hpb=66b2fd11bd1ec6a8a05c4929893c51c7570284fd;p=sifive-blocks.git

diff --git a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
index d7b522f..1e01748 100644
--- a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
+++ b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
@@ -3,8 +3,7 @@ package sifive.blocks.ip.xilinx.vc707mig
 
 import Chisel._
 import chisel3.experimental.{Analog,attach}
-import config._
-import junctions._
+import freechips.rocketchip.config._
 
 // IP VLNV: xilinx.com:customize_ip:vc707mig:1.0
 // Black Box