X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmain%2Fscala%2Futil%2FResetCatchAndSync.scala;fp=src%2Fmain%2Fscala%2Futil%2FResetCatchAndSync.scala;h=0000000000000000000000000000000000000000;hb=d5554bfe95bb64c8afc108ae7a27bff105bf4812;hp=6b483e53a2cce3dde7691545f56213684a0399c3;hpb=402017d34e930788b68edc56162518bd517206a5;p=sifive-blocks.git

diff --git a/src/main/scala/util/ResetCatchAndSync.scala b/src/main/scala/util/ResetCatchAndSync.scala
deleted file mode 100644
index 6b483e5..0000000
--- a/src/main/scala/util/ResetCatchAndSync.scala
+++ /dev/null
@@ -1,42 +0,0 @@
-// See LICENSE for license details.
-package sifive.blocks.util
-
-import Chisel._
-import freechips.rocketchip.util.AsyncResetRegVec
-
-/** Reset: asynchronous assert,
-  *  synchronous de-assert
-  *
-  */
-
-class ResetCatchAndSync (sync: Int = 3) extends Module {
-
-  val io = new Bundle {
-    val sync_reset = Bool(OUTPUT)
-  }
-
-  val reset_n_catch_reg = Module (new AsyncResetRegVec(sync, 0))
-
-  reset_n_catch_reg.io.en := Bool(true)
-  reset_n_catch_reg.io.d  := Cat(Bool(true), reset_n_catch_reg.io.q >> 1)
-
-  io.sync_reset := ~reset_n_catch_reg.io.q(0)
-
-}
-
-object ResetCatchAndSync {
-
-  def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None): Bool = {
-
-    val catcher = Module (new ResetCatchAndSync(sync))
-    if (name.isDefined) {catcher.suggestName(name.get)}
-    catcher.clock := clk
-    catcher.reset := rst
-
-    catcher.io.sync_reset
-  }
-
-  def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name))
-  def apply(clk: Clock, rst: Bool, name: String): Bool = apply(clk, rst, name = Some(name))
-
-}