X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmem%2FBridge.py;h=5f2cc9f40ae912fe51706913c6e6899cbb16df6e;hb=d2fd3b2ec2c265eb9ed3bdcc1db3e4c3feee3846;hp=ea8684e1bba6e25f7b70fa937c0811aedb9c57fb;hpb=5a9a743cfc4517f93e5c94533efa767b92272c59;p=gem5.git

diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py
index ea8684e1b..5f2cc9f40 100644
--- a/src/mem/Bridge.py
+++ b/src/mem/Bridge.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -25,18 +37,18 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
 # Authors: Ali Saidi
+#          Andreas Hansson
 
 from m5.params import *
 from MemObject import MemObject
 
 class Bridge(MemObject):
     type = 'Bridge'
+    cxx_header = "mem/bridge.hh"
     slave = SlavePort('Slave port')
     master = MasterPort('Master port')
     req_size = Param.Int(16, "The number of requests to buffer")
-    resp_size = Param.Int(16, "The number of requests to buffer")
+    resp_size = Param.Int(16, "The number of responses to buffer")
     delay = Param.Latency('0ns', "The latency of this bridge")
-    nack_delay = Param.Latency('0ns', "The latency of this bridge")
-    write_ack = Param.Bool(False, "Should this bridge ack writes")
     ranges = VectorParam.AddrRange([AllMemory],
                                    "Address ranges to pass through the bridge")