X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmem%2FBridge.py;h=b48e1684d7db257965b449525855a2525cc2bd89;hb=2a1309f2134986edcbff846aff5951ec1e8df6e1;hp=8377221cdf2c3dba45243b958ba72a026b72d587;hpb=c432588981c2903fda4b00bf03ada3c2c04063f7;p=gem5.git

diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py
index 8377221cd..b48e1684d 100644
--- a/src/mem/Bridge.py
+++ b/src/mem/Bridge.py
@@ -40,5 +40,7 @@ class Bridge(MemObject):
     delay = Param.Latency('0ns', "The latency of this bridge")
     nack_delay = Param.Latency('0ns', "The latency of this bridge")
     write_ack = Param.Bool(False, "Should this bridge ack writes")
-    fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes")
-    fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes")
+    filter_ranges_a = VectorParam.AddrRange([],
+            "What addresses shouldn't be passed through the side of the bridge")
+    filter_ranges_b = VectorParam.AddrRange([],
+            "What addresses shouldn't be passed through the side of the bridge")