X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmem%2FSConscript;h=ca89418b54ebd8d3a0bc8619ef2d58221755f608;hb=d2fd3b2ec2c265eb9ed3bdcc1db3e4c3feee3846;hp=6692a181ea8b9245d26f248e6e85051bea7cab23;hpb=bd18ac82877072a87745aaf7a104e7bb036c6c66;p=gem5.git

diff --git a/src/mem/SConscript b/src/mem/SConscript
index 6692a181e..ca89418b5 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -30,48 +30,76 @@
 
 Import('*')
 
+# Only build the communication if we have support for protobuf as the
+# tracing relies on it
+if env['HAVE_PROTOBUF']:
+    SimObject('CommMonitor.py')
+    Source('comm_monitor.cc')
+
+SimObject('AddrMapper.py')
 SimObject('Bridge.py')
 SimObject('Bus.py')
 SimObject('MemObject.py')
 
+Source('addr_mapper.cc')
 Source('bridge.cc')
 Source('bus.cc')
+Source('coherent_bus.cc')
 Source('mem_object.cc')
+Source('mport.cc')
+Source('noncoherent_bus.cc')
 Source('packet.cc')
 Source('port.cc')
+Source('packet_queue.cc')
 Source('tport.cc')
-Source('mport.cc')
+Source('port_proxy.cc')
+Source('fs_translating_port_proxy.cc')
+Source('se_translating_port_proxy.cc')
 
 if env['TARGET_ISA'] != 'no':
-    SimObject('PhysicalMemory.py')
-    Source('dram.cc')
+    SimObject('AbstractMemory.py')
+    SimObject('SimpleMemory.py')
+    SimObject('SimpleDRAM.py')
+    Source('abstract_mem.cc')
+    Source('simple_mem.cc')
+    Source('page_table.cc')
     Source('physical.cc')
+    Source('simple_dram.cc')
 
-if env['FULL_SYSTEM']:
-    Source('vport.cc')
-elif env['TARGET_ISA'] != 'no':
-    Source('page_table.cc')
-    Source('translating_port.cc')
+DebugFlag('BaseBus')
+DebugFlag('BusAddrRanges')
+DebugFlag('CoherentBus')
+DebugFlag('NoncoherentBus')
+CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus',
+                     'NoncoherentBus'])
 
-TraceFlag('Bus')
-TraceFlag('BusAddrRanges')
-TraceFlag('BusBridge')
-TraceFlag('LLSC')
-TraceFlag('MMU')
-TraceFlag('MemoryAccess')
+DebugFlag('Bridge')
+DebugFlag('CommMonitor')
+DebugFlag('DRAM')
+DebugFlag('DRAMWR')
+DebugFlag('LLSC')
+DebugFlag('MMU')
+DebugFlag('MemoryAccess')
+DebugFlag('PacketQueue')
 
-TraceFlag('ProtocolTrace')
-TraceFlag('RubyCache')
-TraceFlag('RubyDma')
-TraceFlag('RubyGenerated')
-TraceFlag('RubyMemory')
-TraceFlag('RubyNetwork')
-TraceFlag('RubyQueue')
-TraceFlag('RubyPort')
-TraceFlag('RubySlicc')
-TraceFlag('RubyStorebuffer')
-TraceFlag('RubyTester')
+DebugFlag('ProtocolTrace')
+DebugFlag('RubyCache')
+DebugFlag('RubyCacheTrace')
+DebugFlag('RubyDma')
+DebugFlag('RubyGenerated')
+DebugFlag('RubyMemory')
+DebugFlag('RubyNetwork')
+DebugFlag('RubyPort')
+DebugFlag('RubyPrefetcher')
+DebugFlag('RubyQueue')
+DebugFlag('RubySequencer')
+DebugFlag('RubySlicc')
+DebugFlag('RubySystem')
+DebugFlag('RubyTester')
+DebugFlag('RubyStats')
+DebugFlag('RubyResourceStalls')
 
 CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
-    'RubyGenerated', 'RubySlicc', 'RubyStorebuffer', 'RubyCache', 
-    'RubyMemory', 'RubyDma'])
+    'RubyGenerated', 'RubySlicc', 'RubySystem', 'RubyCache',
+    'RubyMemory', 'RubyDma', 'RubyPort', 'RubySequencer', 'RubyCacheTrace',
+    'RubyPrefetcher'])