X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmem%2FSConscript;h=ca89418b54ebd8d3a0bc8619ef2d58221755f608;hb=d2fd3b2ec2c265eb9ed3bdcc1db3e4c3feee3846;hp=efb3c947a72a63c67139bb2cca24a5e1776144ea;hpb=b00949d88bb3185dfa2e27799de7f90e5a449be8;p=gem5.git diff --git a/src/mem/SConscript b/src/mem/SConscript index efb3c947a..ca89418b5 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -30,14 +30,24 @@ Import('*') +# Only build the communication if we have support for protobuf as the +# tracing relies on it +if env['HAVE_PROTOBUF']: + SimObject('CommMonitor.py') + Source('comm_monitor.cc') + +SimObject('AddrMapper.py') SimObject('Bridge.py') SimObject('Bus.py') SimObject('MemObject.py') +Source('addr_mapper.cc') Source('bridge.cc') Source('bus.cc') +Source('coherent_bus.cc') Source('mem_object.cc') Source('mport.cc') +Source('noncoherent_bus.cc') Source('packet.cc') Source('port.cc') Source('packet_queue.cc') @@ -49,14 +59,24 @@ Source('se_translating_port_proxy.cc') if env['TARGET_ISA'] != 'no': SimObject('AbstractMemory.py') SimObject('SimpleMemory.py') + SimObject('SimpleDRAM.py') Source('abstract_mem.cc') Source('simple_mem.cc') Source('page_table.cc') Source('physical.cc') + Source('simple_dram.cc') -DebugFlag('Bus') +DebugFlag('BaseBus') DebugFlag('BusAddrRanges') -DebugFlag('BusBridge') +DebugFlag('CoherentBus') +DebugFlag('NoncoherentBus') +CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus', + 'NoncoherentBus']) + +DebugFlag('Bridge') +DebugFlag('CommMonitor') +DebugFlag('DRAM') +DebugFlag('DRAMWR') DebugFlag('LLSC') DebugFlag('MMU') DebugFlag('MemoryAccess') @@ -70,12 +90,16 @@ DebugFlag('RubyGenerated') DebugFlag('RubyMemory') DebugFlag('RubyNetwork') DebugFlag('RubyPort') +DebugFlag('RubyPrefetcher') DebugFlag('RubyQueue') DebugFlag('RubySequencer') DebugFlag('RubySlicc') DebugFlag('RubySystem') DebugFlag('RubyTester') +DebugFlag('RubyStats') +DebugFlag('RubyResourceStalls') CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester', 'RubyGenerated', 'RubySlicc', 'RubySystem', 'RubyCache', - 'RubyMemory', 'RubyDma', 'RubyPort', 'RubySequencer', 'RubyCacheTrace']) + 'RubyMemory', 'RubyDma', 'RubyPort', 'RubySequencer', 'RubyCacheTrace', + 'RubyPrefetcher'])