X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmem%2Fcache%2Fblk.hh;h=44691c1229971dbfcb3a7033ddf97304d03fd660;hb=2f4fb22f242b897568d5cbf0e6bc6a77f036f44a;hp=bafb46a89051be7cbdc8a171b387a9b83e17be95;hpb=d56e77c180aeca0ff1ba271378424787345ec0b8;p=gem5.git diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh index bafb46a89..44691c122 100644 --- a/src/mem/cache/blk.hh +++ b/src/mem/cache/blk.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2012-2016 ARM Limited + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2003-2005 The Regents of The University of Michigan * All rights reserved. * @@ -26,37 +38,38 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Erik Hallnor + * Andreas Sandberg */ /** @file * Definitions of a simple cache block class. */ -#ifndef __CACHE_BLK_HH__ -#define __CACHE_BLK_HH__ +#ifndef __MEM_CACHE_BLK_HH__ +#define __MEM_CACHE_BLK_HH__ #include #include "base/printable.hh" -#include "sim/core.hh" // for Tick -#include "arch/isa_traits.hh" // for Addr #include "mem/packet.hh" #include "mem/request.hh" /** * Cache block status bit assignments */ -enum CacheBlkStatusBits { +enum CacheBlkStatusBits : unsigned { /** valid, readable */ - BlkValid = 0x01, + BlkValid = 0x01, /** write permission */ - BlkWritable = 0x02, + BlkWritable = 0x02, + /** read permission (yes, block can be valid but not readable) */ + BlkReadable = 0x04, /** dirty (modified) */ - BlkDirty = 0x04, - /** block was referenced */ - BlkReferenced = 0x10, + BlkDirty = 0x08, /** block was a hardware prefetch yet unaccessed*/ - BlkHWPrefetched = 0x20 + BlkHWPrefetched = 0x20, + /** block holds data from the secure memory space */ + BlkSecure = 0x40, }; /** @@ -66,8 +79,9 @@ enum CacheBlkStatusBits { class CacheBlk { public: - /** The address space ID of this block. */ - int asid; + /** Task Id associated with this block */ + uint32_t task_id; + /** Data block tag value. */ Addr tag; /** @@ -78,8 +92,6 @@ class CacheBlk * referenced by this block. */ uint8_t *data; - /** the number of bytes stored in this block. */ - int size; /** block state: OR of CacheBlkStatusBit */ typedef unsigned State; @@ -87,17 +99,25 @@ class CacheBlk /** The current status of this block. @sa CacheBlockStatusBits */ State status; - /** Which curTick will this block be accessable */ + /** Which curTick() will this block be accessable */ Tick whenReady; /** - * The set this block belongs to. + * The set and way this block belongs to. * @todo Move this into subclasses when we fix CacheTags to use them. */ - int set; + int set, way; + + /** whether this block has been touched */ + bool isTouched; /** Number of references to this block since it was brought in. */ - int refCount; + unsigned refCount; + + /** holds the source requestor ID for this block. */ + int srcMasterId; + + Tick tickInserted; protected: /** @@ -106,18 +126,33 @@ class CacheBlk */ class Lock { public: - int cpuNum; // locking CPU - int threadNum; // locking thread ID within CPU + ContextID contextId; // locking context + Addr lowAddr; // low address of lock range + Addr highAddr; // high address of lock range - // check for matching execution context - bool matchesContext(Request *req) + // check for matching execution context, and an address that + // is within the lock + bool matches(const RequestPtr req) const { - return (cpuNum == req->getCpuNum() && - threadNum == req->getThreadNum()); + Addr req_low = req->getPaddr(); + Addr req_high = req_low + req->getSize() -1; + return (contextId == req->contextId()) && + (req_low >= lowAddr) && (req_high <= highAddr); } - Lock(Request *req) - : cpuNum(req->getCpuNum()), threadNum(req->getThreadNum()) + // check if a request is intersecting and thus invalidating the lock + bool intersects(const RequestPtr req) const + { + Addr req_low = req->getPaddr(); + Addr req_high = req_low + req->getSize() - 1; + + return (req_low <= highAddr) && (req_high >= lowAddr); + } + + Lock(const RequestPtr req) + : contextId(req->contextId()), + lowAddr(req->getPaddr()), + highAddr(lowAddr + req->getSize() - 1) { } }; @@ -129,40 +164,40 @@ class CacheBlk public: CacheBlk() - : asid(-1), tag(0), data(0) ,size(0), status(0), whenReady(0), - set(-1), refCount(0) + : task_id(ContextSwitchTaskId::Unknown), + tag(0), data(0), status(0), whenReady(0), + set(-1), way(-1), isTouched(false), refCount(0), + srcMasterId(Request::invldMasterId), + tickInserted(0) {} + CacheBlk(const CacheBlk&) = delete; + CacheBlk& operator=(const CacheBlk&) = delete; + /** - * Copy the state of the given block into this one. - * @param rhs The block to copy. - * @return a const reference to this block. + * Checks the write permissions of this block. + * @return True if the block is writable. */ - const CacheBlk& operator=(const CacheBlk& rhs) + bool isWritable() const { - asid = rhs.asid; - tag = rhs.tag; - data = rhs.data; - size = rhs.size; - status = rhs.status; - whenReady = rhs.whenReady; - set = rhs.set; - refCount = rhs.refCount; - return *this; + const State needed_bits = BlkWritable | BlkValid; + return (status & needed_bits) == needed_bits; } /** - * Checks the write permissions of this block. - * @return True if the block is writable. + * Checks the read permissions of this block. Note that a block + * can be valid but not readable if there is an outstanding write + * upgrade miss. + * @return True if the block is readable. */ - bool isWritable() const + bool isReadable() const { - const int needed_bits = BlkWritable | BlkValid; + const State needed_bits = BlkReadable | BlkValid; return (status & needed_bits) == needed_bits; } /** - * Checks that a block is valid (readable). + * Checks that a block is valid. * @return True if the block is valid. */ bool isValid() const @@ -171,21 +206,22 @@ class CacheBlk } /** - * Check to see if a block has been written. - * @return True if the block is dirty. + * Invalidate the block and clear all state. */ - bool isDirty() const + void invalidate() { - return (status & BlkDirty) != 0; + status = 0; + isTouched = false; + lockList.clear(); } /** - * Check if this block has been referenced. - * @return True if the block has been referenced. + * Check to see if a block has been written. + * @return True if the block is dirty. */ - bool isReferenced() const + bool isDirty() const { - return (status & BlkReferenced) != 0; + return (status & BlkDirty) != 0; } /** @@ -193,28 +229,100 @@ class CacheBlk * be touched. * @return True if the block was a hardware prefetch, unaccesed. */ - bool isPrefetch() const + bool wasPrefetched() const { return (status & BlkHWPrefetched) != 0; } /** - * Track the fact that a local locked was issued to the block. If - * multiple LLs get issued from the same context we could have - * redundant records on the list, but that's OK, as they'll all - * get blown away at the next store. + * Check if this block holds data from the secure memory space. + * @return True if the block holds data from the secure memory space. + */ + bool isSecure() const + { + return (status & BlkSecure) != 0; + } + + /** + * Track the fact that a local locked was issued to the + * block. Invalidate any previous LL to the same address. */ void trackLoadLocked(PacketPtr pkt) { - assert(pkt->isLocked()); - lockList.push_front(Lock(pkt->req)); + assert(pkt->isLLSC()); + auto l = lockList.begin(); + while (l != lockList.end()) { + if (l->intersects(pkt->req)) + l = lockList.erase(l); + else + ++l; + } + + lockList.emplace_front(pkt->req); } /** - * Clear the list of valid load locks. Should be called whenever - * block is written to or invalidated. + * Clear the any load lock that intersect the request, and is from + * a different context. */ - void clearLoadLocks() { lockList.clear(); } + void clearLoadLocks(RequestPtr req) + { + auto l = lockList.begin(); + while (l != lockList.end()) { + if (l->intersects(req) && l->contextId != req->contextId()) { + l = lockList.erase(l); + } else { + ++l; + } + } + } + + /** + * Pretty-print a tag, and interpret state bits to readable form + * including mapping to a MOESI state. + * + * @return string with basic state information + */ + std::string print() const + { + /** + * state M O E S I + * writable 1 0 1 0 0 + * dirty 1 1 0 0 0 + * valid 1 1 1 1 0 + * + * state writable dirty valid + * M 1 1 1 + * O 0 1 1 + * E 1 0 1 + * S 0 0 1 + * I 0 0 0 + * + * Note that only one cache ever has a block in Modified or + * Owned state, i.e., only one cache owns the block, or + * equivalently has the BlkDirty bit set. However, multiple + * caches on the same path to memory can have a block in the + * Exclusive state (despite the name). Exclusive means this + * cache has the only copy at this level of the hierarchy, + * i.e., there may be copies in caches above this cache (in + * various states), but there are no peers that have copies on + * this branch of the hierarchy, and no caches at or above + * this level on any other branch have copies either. + **/ + unsigned state = isWritable() << 2 | isDirty() << 1 | isValid(); + char s = '?'; + switch (state) { + case 0b111: s = 'M'; break; + case 0b011: s = 'O'; break; + case 0b101: s = 'E'; break; + case 0b001: s = 'S'; break; + case 0b000: s = 'I'; break; + default: s = 'T'; break; // @TODO add other types + } + return csprintf("state: %x (%c) valid: %d writable: %d readable: %d " + "dirty: %d tag: %x", status, s, isValid(), + isWritable(), isReadable(), isDirty(), tag); + } /** * Handle interaction of load-locked operations and stores. @@ -223,31 +331,42 @@ class CacheBlk */ bool checkWrite(PacketPtr pkt) { - Request *req = pkt->req; - if (pkt->isLocked()) { + assert(pkt->isWrite()); + + // common case + if (!pkt->isLLSC() && lockList.empty()) + return true; + + RequestPtr req = pkt->req; + + if (pkt->isLLSC()) { // it's a store conditional... have to check for matching // load locked. bool success = false; - for (std::list::iterator i = lockList.begin(); - i != lockList.end(); ++i) - { - if (i->matchesContext(req)) { - // it's a store conditional, and as far as the memory - // system can tell, the requesting context's lock is - // still valid. + auto l = lockList.begin(); + while (!success && l != lockList.end()) { + if (l->matches(pkt->req)) { + // it's a store conditional, and as far as the + // memory system can tell, the requesting + // context's lock is still valid. success = true; - break; + lockList.erase(l); + } else { + ++l; } } req->setExtraData(success ? 1 : 0); - clearLoadLocks(); + // clear any intersected locks from other contexts (our LL + // should already have cleared them) + clearLoadLocks(req); return success; } else { - // for *all* stores (conditional or otherwise) we have to - // clear the list of load-locks as they're all invalid now. - clearLoadLocks(); + // a normal write, if there is any lock not from this + // context we clear the list, thus for a private cache we + // never clear locks on normal writes + clearLoadLocks(req); return true; } } @@ -269,6 +388,20 @@ class CacheBlkPrintWrapper : public Printable const std::string &prefix = "") const; }; +/** + * Base class for cache block visitor, operating on the cache block + * base class (later subclassed for the various tag classes). This + * visitor class is used as part of the forEachBlk interface in the + * tag classes. + */ +class CacheBlkVisitor +{ + public: + + CacheBlkVisitor() {} + virtual ~CacheBlkVisitor() {} + virtual bool operator()(CacheBlk &blk) = 0; +}; -#endif //__CACHE_BLK_HH__ +#endif //__MEM_CACHE_BLK_HH__