X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmem%2Fcache%2Fcache.hh;h=06fce1a71b7b50f0e0337fb93e0364fcb00c880e;hb=83af0fdcf57175adf8077c51e9ba872dd2c04b76;hp=ec5b800a8e74e90145fe5dd707e28e71ff76ef75;hpb=55e59e26c1a7acd8715262999451c451fc50b480;p=gem5.git diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index ec5b800a8..06fce1a71 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -28,6 +28,7 @@ * Authors: Erik Hallnor * Dave Greene * Steve Reinhardt + * Ron Dreslinski */ /** @@ -38,15 +39,18 @@ #ifndef __CACHE_HH__ #define __CACHE_HH__ +#include "base/compression/base.hh" #include "base/misc.hh" // fatal, panic, and warn #include "cpu/smt.hh" // SMT_MAX_THREADS #include "mem/cache/base_cache.hh" -#include "mem/cache/prefetch/prefetcher.hh" +#include "mem/cache/cache_blk.hh" +#include "mem/cache/miss/mshr.hh" -//Forward decleration -class MSHR; +#include "sim/eventq.hh" +//Forward decleration +class BasePrefetcher; /** * A template-policy based cache. The behavior of the cache can be altered by @@ -55,31 +59,82 @@ class MSHR; * @sa MissQueue. Coherence handles all coherence policy details @sa * UniCoherence, SimpleMultiCoherence. */ -template +template class Cache : public BaseCache { public: /** Define the type of cache block to use. */ typedef typename TagStore::BlkType BlkType; + /** A typedef for a list of BlkType pointers. */ + typedef typename TagStore::BlkList BlkList; bool prefetchAccess; + protected: + class CpuSidePort : public CachePort + { + public: + CpuSidePort(const std::string &_name, + Cache *_cache); + + // BaseCache::CachePort just has a BaseCache *; this function + // lets us get back the type info we lost when we stored the + // cache pointer there. + Cache *myCache() { + return static_cast *>(cache); + } + + virtual void getDeviceAddressRanges(AddrRangeList &resp, + bool &snoop); + + virtual bool recvTiming(PacketPtr pkt); + + virtual Tick recvAtomic(PacketPtr pkt); + + virtual void recvFunctional(PacketPtr pkt); + }; + + class MemSidePort : public CachePort + { + public: + MemSidePort(const std::string &_name, + Cache *_cache); + + // BaseCache::CachePort just has a BaseCache *; this function + // lets us get back the type info we lost when we stored the + // cache pointer there. + Cache *myCache() { + return static_cast *>(cache); + } + + void sendPacket(); + + void processSendEvent(); + + virtual void getDeviceAddressRanges(AddrRangeList &resp, + bool &snoop); + + virtual bool recvTiming(PacketPtr pkt); + + virtual void recvRetry(); + + virtual Tick recvAtomic(PacketPtr pkt); + + virtual void recvFunctional(PacketPtr pkt); + + typedef EventWrapper + SendEvent; + }; + /** Tag and data Storage */ TagStore *tags; - /** Miss and Writeback handler */ - Buffering *missQueue; + /** Coherence protocol. */ Coherence *coherence; /** Prefetcher */ - Prefetcher *prefetcher; - - /** Do fast copies in this cache. */ - bool doCopy; - - /** Block on a delayed copy. */ - bool blockOnCopy; + BasePrefetcher *prefetcher; /** * The clock ratio of the outgoing bus. @@ -98,23 +153,71 @@ class Cache : public BaseCache */ int hitLatency; - /** - * A permanent mem req to always be used to cause invalidations. - * Used to append to target list, to cause an invalidation. - */ - Packet * invalidatePkt; + /** + * Can this cache should allocate a block on a line-sized write miss. + */ + const bool doFastWrites; + + const bool prefetchMiss; + + /** + * Handle a replacement for the given request. + * @param blk A pointer to the block, usually NULL + * @param pkt The memory request to satisfy. + * @param new_state The new state of the block. + * @param writebacks A list to store any generated writebacks. + */ + BlkType* doReplacement(BlkType *blk, PacketPtr pkt, + CacheBlk::State new_state, PacketList &writebacks); + + /** + * Does all the processing necessary to perform the provided request. + * @param pkt The memory request to perform. + * @param lat The latency of the access. + * @param writebacks List for any writebacks that need to be performed. + * @param update True if the replacement data should be updated. + * @return Pointer to the cache block touched by the request. NULL if it + * was a miss. + */ + bool access(PacketPtr pkt, BlkType *&blk, int &lat); /** - * Temporarily move a block into a MSHR. - * @todo Remove this when LSQ/SB are fixed and implemented in memtest. + *Handle doing the Compare and Swap function for SPARC. */ - void pseudoFill(Addr addr, int asid); + void cmpAndSwap(BlkType *blk, PacketPtr pkt); /** - * Temporarily move a block into an existing MSHR. - * @todo Remove this when LSQ/SB are fixed and implemented in memtest. + * Populates a cache block and handles all outstanding requests for the + * satisfied fill request. This version takes two memory requests. One + * contains the fill data, the other is an optional target to satisfy. + * Used for Cache::probe. + * @param pkt The memory request with the fill data. + * @param blk The cache block if it already exists. + * @param writebacks List for any writebacks that need to be performed. + * @return Pointer to the new cache block. */ - void pseudoFill(MSHR *mshr); + BlkType *handleFill(PacketPtr pkt, BlkType *blk, + PacketList &writebacks); + + bool satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk); + bool satisfyTarget(MSHR::Target *target, BlkType *blk); + bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk); + + void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data); + + /** + * Sets the blk to the new state. + * @param blk The cache block being snooped. + * @param new_state The new coherence state for the block. + */ + void handleSnoop(PacketPtr ptk, BlkType *blk, bool is_timing); + + /** + * Create a writeback request for the given block. + * @param blk The block to writeback. + * @return The writeback request for the block. + */ + PacketPtr writebackBlk(BlkType *blk); public: @@ -122,23 +225,24 @@ class Cache : public BaseCache { public: TagStore *tags; - Buffering *missQueue; Coherence *coherence; - bool doCopy; - bool blockOnCopy; BaseCache::Params baseParams; - Prefetcher *prefetcher; + BasePrefetcher*prefetcher; bool prefetchAccess; - int hitLatency; - - Params(TagStore *_tags, Buffering *mq, Coherence *coh, - bool do_copy, BaseCache::Params params, - Prefetcher *_prefetcher, - bool prefetch_access, int hit_latency) - : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy), - blockOnCopy(false), baseParams(params), + const bool doFastWrites; + const bool prefetchMiss; + + Params(TagStore *_tags, Coherence *coh, + BaseCache::Params params, + BasePrefetcher *_prefetcher, + bool prefetch_access, int hit_latency, + bool do_fast_writes, + bool prefetch_miss) + : tags(_tags), coherence(coh), + baseParams(params), prefetcher(_prefetcher), prefetchAccess(prefetch_access), - hitLatency(hit_latency) + doFastWrites(do_fast_writes), + prefetchMiss(prefetch_miss) { } }; @@ -146,123 +250,110 @@ class Cache : public BaseCache /** Instantiates a basic cache object. */ Cache(const std::string &_name, Params ¶ms); - virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, - bool isCpuSide); - - virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide); - - virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide); - - virtual void recvStatusChange(Port::Status status, bool isCpuSide); + virtual Port *getPort(const std::string &if_name, int idx = -1); + virtual void deletePortRefs(Port *p); void regStats(); /** * Performs the access specified by the request. - * @param req The request to perform. + * @param pkt The request to perform. * @return The result of the access. */ - bool access(Packet * &pkt); + bool timingAccess(PacketPtr pkt); /** - * Selects a request to send on the bus. - * @return The memory request to service. + * Performs the access specified by the request. + * @param pkt The request to perform. + * @return The result of the access. */ - virtual Packet * getPacket(); + Tick atomicAccess(PacketPtr pkt); /** - * Was the request was sent successfully? - * @param req The request. - * @param success True if the request was sent successfully. + * Performs the access specified by the request. + * @param pkt The request to perform. + * @return The result of the access. */ - virtual void sendResult(Packet * &pkt, bool success); + void functionalAccess(PacketPtr pkt, CachePort *otherSidePort); /** * Handles a response (cache line fill/write ack) from the bus. - * @param req The request being responded to. + * @param pkt The request being responded to. */ - void handleResponse(Packet * &pkt); + void handleResponse(PacketPtr pkt); /** - * Start handling a copy transaction. - * @param req The copy request to perform. + * Snoops bus transactions to maintain coherence. + * @param pkt The current bus transaction. */ - void startCopy(Packet * &pkt); + void snoopTiming(PacketPtr pkt); /** - * Handle a delayed copy transaction. - * @param req The delayed copy request to continue. - * @param addr The address being responded to. - * @param blk The block of the current response. - * @param mshr The mshr being handled. + * Snoop for the provided request in the cache and return the estimated + * time of completion. + * @param pkt The memory request to snoop + * @return The estimated completion time. */ - void handleCopy(Packet * &pkt, Addr addr, BlkType *blk, MSHR *mshr); + Tick snoopAtomic(PacketPtr pkt); /** - * Selects a coherence message to forward to lower levels of the hierarchy. - * @return The coherence message to forward. + * Squash all requests associated with specified thread. + * intended for use by I-cache. + * @param threadNum The thread to squash. */ - virtual Packet * getCoherencePacket(); + void squash(int threadNum); /** - * Snoops bus transactions to maintain coherence. - * @param req The current bus transaction. + * Allocate a new MSHR or write buffer to handle a miss. + * @param pkt The access that missed. + * @param time The time to continue processing the miss. + * @param isFill Whether to fetch & allocate a block + * or just forward the request. */ - void snoop(Packet * &pkt); + MSHR *allocateBuffer(PacketPtr pkt, Tick time, bool requestBus); - void snoopResponse(Packet * &pkt); + /** + * Selects a outstanding request to service. + * @return The request to service, NULL if none found. + */ + PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk, + bool needsExclusive); + MSHR *getNextMSHR(); + PacketPtr getTimingPacket(); /** - * Invalidates the block containing address if found. - * @param addr The address to look for. - * @param asid The address space ID of the address. - * @todo Is this function necessary? + * Marks a request as in service (sent on the bus). This can have side + * effect since storage for no response commands is deallocated once they + * are successfully sent. + * @param pkt The request that was sent on the bus. */ - void invalidateBlk(Addr addr, int asid); + void markInService(MSHR *mshr); /** - * Aquash all requests associated with specified thread. - * intended for use by I-cache. - * @param req->getThreadNum()ber The thread to squash. + * Perform the given writeback request. + * @param pkt The writeback request. */ - void squash(int threadNum) - { - missQueue->squash(threadNum); - } + void doWriteback(PacketPtr pkt); /** - * Return the number of outstanding misses in a Cache. - * Default returns 0. - * - * @retval unsigned The number of missing still outstanding. + * Return whether there are any outstanding misses. */ - unsigned outstandingMisses() const + bool outstandingMisses() const { - return missQueue->getMisses(); + return mshrQueue.allocated != 0; } - /** - * Perform the access specified in the request and return the estimated - * time of completion. This function can either update the hierarchy state - * or just perform the access wherever the data is found depending on the - * state of the update flag. - * @param req The memory request to satisfy - * @param update If true, update the hierarchy, otherwise just perform the - * request. - * @return The estimated completion time. - */ - Tick probe(Packet * &pkt, bool update); + CacheBlk *findBlock(Addr addr) { + return tags->findBlock(addr); + } - /** - * Snoop for the provided request in the cache and return the estimated - * time of completion. - * @todo Can a snoop probe not change state? - * @param req The memory request to satisfy - * @param update If true, update the hierarchy, otherwise just perform the - * request. - * @return The estimated completion time. - */ - Tick snoopProbe(Packet * &pkt, bool update); + bool inCache(Addr addr) { + return (tags->findBlock(addr) != 0); + } + + bool inMissQueue(Addr addr) { + return (mshrQueue.findMatch(addr) != 0); + } }; #endif // __CACHE_HH__