X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmem%2Fcache%2Fcache.hh;h=33c5a2412a04a32988b781dd7e958c4156f21b0a;hb=2dd82da9b8275fab6235e2e6ff4859978a225db4;hp=1ed138bb5e9ee65d38d60d899acec15f0b3b58f0;hpb=39a055645f77e0fa7bf49406635dba6bd65e361f;p=gem5.git diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 1ed138bb5..33c5a2412 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2012-2018 ARM Limited + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2002-2005 The Regents of The University of Michigan * All rights reserved. * @@ -29,301 +41,137 @@ * Dave Greene * Steve Reinhardt * Ron Dreslinski + * Andreas Hansson */ /** * @file - * Describes a cache based on template policies. + * Describes a cache */ -#ifndef __CACHE_HH__ -#define __CACHE_HH__ +#ifndef __MEM_CACHE_CACHE_HH__ +#define __MEM_CACHE_CACHE_HH__ -#include "base/misc.hh" // fatal, panic, and warn +#include +#include + +#include "base/types.hh" #include "mem/cache/base.hh" -#include "mem/cache/blk.hh" -#include "mem/cache/mshr.hh" -#include "sim/eventq.hh" +#include "mem/packet.hh" -//Forward decleration -class BasePrefetcher; +class CacheBlk; +struct CacheParams; +class MSHR; /** - * A template-policy based cache. The behavior of the cache can be altered by - * supplying different template policies. TagStore handles all tag and data - * storage @sa TagStore. + * A coherent cache that can be arranged in flexible topologies. */ -template class Cache : public BaseCache { - public: - /** Define the type of cache block to use. */ - typedef typename TagStore::BlkType BlkType; - /** A typedef for a list of BlkType pointers. */ - typedef typename TagStore::BlkList BlkList; - protected: - - class CpuSidePort : public CachePort - { - public: - CpuSidePort(const std::string &_name, - Cache *_cache, - const std::string &_label); - - // BaseCache::CachePort just has a BaseCache *; this function - // lets us get back the type info we lost when we stored the - // cache pointer there. - Cache *myCache() { - return static_cast *>(cache); - } - - virtual void getDeviceAddressRanges(AddrRangeList &resp, - bool &snoop); - - virtual bool recvTiming(PacketPtr pkt); - - virtual Tick recvAtomic(PacketPtr pkt); - - virtual void recvFunctional(PacketPtr pkt); - }; - - class MemSidePort : public CachePort - { - public: - MemSidePort(const std::string &_name, - Cache *_cache, - const std::string &_label); - - // BaseCache::CachePort just has a BaseCache *; this function - // lets us get back the type info we lost when we stored the - // cache pointer there. - Cache *myCache() { - return static_cast *>(cache); - } - - void sendPacket(); - - void processSendEvent(); - - virtual void getDeviceAddressRanges(AddrRangeList &resp, - bool &snoop); - - virtual bool recvTiming(PacketPtr pkt); - - virtual void recvRetry(); - - virtual Tick recvAtomic(PacketPtr pkt); - - virtual void recvFunctional(PacketPtr pkt); - - typedef EventWrapper - SendEvent; - }; - - /** Tag and data Storage */ - TagStore *tags; - - /** Prefetcher */ - BasePrefetcher *prefetcher; - - /** Temporary cache block for occasional transitory use */ - BlkType *tempBlock; - /** * This cache should allocate a block on a line-sized write miss. */ const bool doFastWrites; /** - * Notify the prefetcher on every access, not just misses. - */ - const bool prefetchOnAccess; - - /** - * Does all the processing necessary to perform the provided request. - * @param pkt The memory request to perform. - * @param lat The latency of the access. - * @param writebacks List for any writebacks that need to be performed. - * @param update True if the replacement data should be updated. - * @return Boolean indicating whether the request was satisfied. - */ - bool access(PacketPtr pkt, BlkType *&blk, - int &lat, PacketList &writebacks); - - /** - *Handle doing the Compare and Swap function for SPARC. - */ - void cmpAndSwap(BlkType *blk, PacketPtr pkt); - - /** - * Find a block frame for new block at address addr, assuming that - * the block is not currently in the cache. Append writebacks if - * any to provided packet list. Return free block frame. May - * return NULL if there are no replaceable blocks at the moment. + * Store the outstanding requests that we are expecting snoop + * responses from so we can determine which snoop responses we + * generated and which ones were merely forwarded. */ - BlkType *allocateBlock(Addr addr, PacketList &writebacks); + std::unordered_set outstandingSnoop; + protected: /** - * Populates a cache block and handles all outstanding requests for the - * satisfied fill request. This version takes two memory requests. One - * contains the fill data, the other is an optional target to satisfy. - * @param pkt The memory request with the fill data. - * @param blk The cache block if it already exists. - * @param writebacks List for any writebacks that need to be performed. - * @return Pointer to the new cache block. + * Turn line-sized writes into WriteInvalidate transactions. */ - BlkType *handleFill(PacketPtr pkt, BlkType *blk, - PacketList &writebacks); + void promoteWholeLineWrites(PacketPtr pkt); - void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk, - bool deferred_response = false, - bool pending_downgrade = false); - bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk); + bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, + PacketList &writebacks) override; - void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data, - bool already_copied, bool pending_inval); + void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, + Tick request_time) override; - /** - * Sets the blk to the new state. - * @param blk The cache block being snooped. - * @param new_state The new coherence state for the block. - */ - void handleSnoop(PacketPtr ptk, BlkType *blk, - bool is_timing, bool is_deferred, bool pending_inval); + void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, + Tick forward_time, + Tick request_time) override; - /** - * Create a writeback request for the given block. - * @param blk The block to writeback. - * @return The writeback request for the block. - */ - PacketPtr writebackBlk(BlkType *blk); + void recvTimingReq(PacketPtr pkt) override; - public: - /** Instantiates a basic cache object. */ - Cache(const Params *p, TagStore *tags, BasePrefetcher *prefetcher); + void doWritebacks(PacketList& writebacks, Tick forward_time) override; - virtual Port *getPort(const std::string &if_name, int idx = -1); - virtual void deletePortRefs(Port *p); + void doWritebacksAtomic(PacketList& writebacks) override; - void regStats(); + void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, + CacheBlk *blk) override; - /** - * Performs the access specified by the request. - * @param pkt The request to perform. - * @return The result of the access. - */ - bool timingAccess(PacketPtr pkt); - - /** - * Performs the access specified by the request. - * @param pkt The request to perform. - * @return The result of the access. - */ - Tick atomicAccess(PacketPtr pkt); + void recvTimingSnoopReq(PacketPtr pkt) override; - /** - * Performs the access specified by the request. - * @param pkt The request to perform. - * @return The result of the access. - */ - void functionalAccess(PacketPtr pkt, CachePort *incomingPort, - CachePort *otherSidePort); + void recvTimingSnoopResp(PacketPtr pkt) override; - /** - * Handles a response (cache line fill/write ack) from the bus. - * @param pkt The request being responded to. - */ - void handleResponse(PacketPtr pkt); + Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, + PacketList &writebacks) override; - /** - * Snoops bus transactions to maintain coherence. - * @param pkt The current bus transaction. - */ - void snoopTiming(PacketPtr pkt); + Tick recvAtomic(PacketPtr pkt) override; - /** - * Snoop for the provided request in the cache and return the estimated - * time of completion. - * @param pkt The memory request to snoop - * @return The estimated completion time. - */ - Tick snoopAtomic(PacketPtr pkt); + Tick recvAtomicSnoop(PacketPtr pkt) override; - /** - * Squash all requests associated with specified thread. - * intended for use by I-cache. - * @param threadNum The thread to squash. - */ - void squash(int threadNum); + void satisfyRequest(PacketPtr pkt, CacheBlk *blk, + bool deferred_response = false, + bool pending_downgrade = false) override; - /** - * Generate an appropriate downstream bus request packet for the - * given parameters. - * @param cpu_pkt The upstream request that needs to be satisfied. - * @param blk The block currently in the cache corresponding to - * cpu_pkt (NULL if none). - * @param needsExclusive Indicates that an exclusive copy is required - * even if the request in cpu_pkt doesn't indicate that. - * @return A new Packet containing the request, or NULL if the - * current request in cpu_pkt should just be forwarded on. - */ - PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk, - bool needsExclusive); + void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, + bool already_copied, bool pending_inval); /** - * Return the next MSHR to service, either a pending miss from the - * mshrQueue, a buffered write from the write buffer, or something - * from the prefetcher. This function is responsible for - * prioritizing among those sources on the fly. + * Perform an upward snoop if needed, and update the block state + * (possibly invalidating the block). Also create a response if required. + * + * @param pkt Snoop packet + * @param blk Cache block being snooped + * @param is_timing Timing or atomic for the response + * @param is_deferred Is this a deferred snoop or not? + * @param pending_inval Do we have a pending invalidation? + * + * @return The snoop delay incurred by the upwards snoop */ - MSHR *getNextMSHR(); + uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk, + bool is_timing, bool is_deferred, bool pending_inval); - /** - * Selects an outstanding request to service. Called when the - * cache gets granted the downstream bus in timing mode. - * @return The request to service, NULL if none found. - */ - PacketPtr getTimingPacket(); + M5_NODISCARD PacketPtr evictBlock(CacheBlk *blk) override; /** - * Marks a request as in service (sent on the bus). This can have side - * effect since storage for no response commands is deallocated once they - * are successfully sent. - * @param pkt The request that was sent on the bus. + * Create a CleanEvict request for the given block. + * + * @param blk The block to evict. + * @return The CleanEvict request for the block. */ - void markInService(MSHR *mshr, PacketPtr pkt = 0); + PacketPtr cleanEvictBlk(CacheBlk *blk); - /** - * Perform the given writeback request. - * @param pkt The writeback request. - */ - void doWriteback(PacketPtr pkt); + PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, + bool needs_writable, + bool is_whole_line_write) const override; /** - * Return whether there are any outstanding misses. + * Send up a snoop request and find cached copies. If cached copies are + * found, set the BLOCK_CACHED flag in pkt. */ - bool outstandingMisses() const - { - return mshrQueue.allocated != 0; - } + bool isCachedAbove(PacketPtr pkt, bool is_timing = true); - CacheBlk *findBlock(Addr addr) { - return tags->findBlock(addr); - } - - bool inCache(Addr addr) { - return (tags->findBlock(addr) != 0); - } - - bool inMissQueue(Addr addr) { - return (mshrQueue.findMatch(addr) != 0); - } + public: + /** Instantiates a basic cache object. */ + Cache(const CacheParams *p); /** - * Find next request ready time from among possible sources. + * Take an MSHR, turn it into a suitable downstream packet, and + * send it out. This construct allows a queue entry to choose a suitable + * approach based on its type. + * + * @param mshr The MSHR to turn into a packet and send + * @return True if the port is waiting for a retry */ - Tick nextMSHRReadyTime(); + bool sendMSHRQueuePacket(MSHR* mshr) override; }; -#endif // __CACHE_HH__ +#endif // __MEM_CACHE_CACHE_HH__