X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmem%2Fcache%2Fcache.hh;h=4c70d3a4040436812c05af586b602663249d0e87;hb=a262908acc0a641700a03fcea89c48133f0467cd;hp=60f3650e7222260720fe01e747e932413aaf91ca;hpb=aefe9cc624902fe26535028f86ba3a45f555bcf0;p=gem5.git diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 60f3650e7..4c70d3a40 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2013 ARM Limited + * Copyright (c) 2012-2014 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -56,6 +56,7 @@ #include "mem/cache/base.hh" #include "mem/cache/blk.hh" #include "mem/cache/mshr.hh" +#include "mem/cache/tags/base.hh" #include "sim/eventq.hh" //Forward decleration @@ -66,17 +67,14 @@ class BasePrefetcher; * supplying different template policies. TagStore handles all tag and data * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System" */ -template class Cache : public BaseCache { public: - /** Define the type of cache block to use. */ - typedef typename TagStore::BlkType BlkType; - /** A typedef for a list of BlkType pointers. */ - typedef typename TagStore::BlkList BlkList; + + /** A typedef for a list of CacheBlk pointers. */ + typedef std::list BlkList; protected: - typedef CacheBlkVisitorWrapper, BlkType> WrappedBlkVisitor; /** * The CPU-side port extends the base cache slave port with access @@ -87,7 +85,7 @@ class Cache : public BaseCache private: // a pointer to our specific cache implementation - Cache *cache; + Cache *cache; protected: @@ -103,7 +101,7 @@ class Cache : public BaseCache public: - CpuSidePort(const std::string &_name, Cache *_cache, + CpuSidePort(const std::string &_name, Cache *_cache, const std::string &_label); }; @@ -114,18 +112,21 @@ class Cache : public BaseCache * current MSHR status. This queue has a pointer to our specific * cache implementation and is used by the MemSidePort. */ - class MemSidePacketQueue : public MasterPacketQueue + class CacheReqPacketQueue : public ReqPacketQueue { protected: - Cache &cache; + Cache &cache; + SnoopRespPacketQueue &snoopRespQueue; public: - MemSidePacketQueue(Cache &cache, MasterPort &port, - const std::string &label) : - MasterPacketQueue(cache, port, label), cache(cache) { } + CacheReqPacketQueue(Cache &cache, MasterPort &port, + SnoopRespPacketQueue &snoop_resp_queue, + const std::string &label) : + ReqPacketQueue(cache, port, label), cache(cache), + snoopRespQueue(snoop_resp_queue) { } /** * Override the normal sendDeferredPacket and do not only @@ -145,10 +146,12 @@ class Cache : public BaseCache private: /** The cache-specific queue. */ - MemSidePacketQueue _queue; + CacheReqPacketQueue _reqQueue; + + SnoopRespPacketQueue _snoopRespQueue; // a pointer to our specific cache implementation - Cache *cache; + Cache *cache; protected: @@ -162,24 +165,29 @@ class Cache : public BaseCache public: - MemSidePort(const std::string &_name, Cache *_cache, + MemSidePort(const std::string &_name, Cache *_cache, const std::string &_label); }; /** Tag and data Storage */ - TagStore *tags; + BaseTags *tags; /** Prefetcher */ BasePrefetcher *prefetcher; /** Temporary cache block for occasional transitory use */ - BlkType *tempBlock; + CacheBlk *tempBlock; /** * This cache should allocate a block on a line-sized write miss. */ const bool doFastWrites; + /** + * Turn line-sized writes into WriteInvalidate transactions. + */ + void promoteWholeLineWrites(PacketPtr pkt); + /** * Notify the prefetcher on every access, not just misses. */ @@ -195,18 +203,18 @@ class Cache : public BaseCache /** * Does all the processing necessary to perform the provided request. * @param pkt The memory request to perform. + * @param blk The cache block to be updated. * @param lat The latency of the access. * @param writebacks List for any writebacks that need to be performed. - * @param update True if the replacement data should be updated. * @return Boolean indicating whether the request was satisfied. */ - bool access(PacketPtr pkt, BlkType *&blk, + bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, PacketList &writebacks); /** *Handle doing the Compare and Swap function for SPARC. */ - void cmpAndSwap(BlkType *blk, PacketPtr pkt); + void cmpAndSwap(CacheBlk *blk, PacketPtr pkt); /** * Find a block frame for new block at address addr targeting the @@ -215,7 +223,7 @@ class Cache : public BaseCache * list. Return free block frame. May return NULL if there are * no replaceable blocks at the moment. */ - BlkType *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks); + CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks); /** * Populates a cache block and handles all outstanding requests for the @@ -226,7 +234,7 @@ class Cache : public BaseCache * @param writebacks List for any writebacks that need to be performed. * @return Pointer to the new cache block. */ - BlkType *handleFill(PacketPtr pkt, BlkType *blk, + CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks); @@ -237,6 +245,11 @@ class Cache : public BaseCache */ bool recvTimingReq(PacketPtr pkt); + /** + * Insert writebacks into the write buffer + */ + void doWritebacks(PacketList& writebacks, Tick forward_time); + /** * Handles a response (cache line fill/write ack) from the bus. * @param pkt The response packet @@ -277,12 +290,12 @@ class Cache : public BaseCache */ void functionalAccess(PacketPtr pkt, bool fromCpuSide); - void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk, + void satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk, bool deferred_response = false, bool pending_downgrade = false); - bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk); + bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, CacheBlk *blk); - void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data, + void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, bool already_copied, bool pending_inval); /** @@ -290,7 +303,7 @@ class Cache : public BaseCache * @param blk The cache block being snooped. * @param new_state The new coherence state for the block. */ - void handleSnoop(PacketPtr ptk, BlkType *blk, + void handleSnoop(PacketPtr ptk, CacheBlk *blk, bool is_timing, bool is_deferred, bool pending_inval); /** @@ -298,7 +311,14 @@ class Cache : public BaseCache * @param blk The block to writeback. * @return The writeback request for the block. */ - PacketPtr writebackBlk(BlkType *blk); + PacketPtr writebackBlk(CacheBlk *blk); + + /** + * Create a CleanEvict request for the given block. + * @param blk The block to evict. + * @return The CleanEvict request for the block. + */ + PacketPtr cleanEvictBlk(CacheBlk *blk); void memWriteback(); @@ -311,7 +331,7 @@ class Cache : public BaseCache * * \return Always returns true. */ - bool writebackVisitor(BlkType &blk); + bool writebackVisitor(CacheBlk &blk); /** * Cache block visitor that invalidates all blocks in the cache. * @@ -319,19 +339,7 @@ class Cache : public BaseCache * * \return Always returns true. */ - bool invalidateVisitor(BlkType &blk); - - /** - * Flush a cache line due to an uncacheable memory access to the - * line. - * - * @note This shouldn't normally happen, but we need to handle it - * since some architecture models don't implement cache - * maintenance operations. We won't even try to get a decent - * timing here since the line should have been flushed earlier by - * a cache maintenance operation. - */ - void uncacheableFlush(PacketPtr pkt); + bool invalidateVisitor(CacheBlk &blk); /** * Squash all requests associated with specified thread. @@ -351,7 +359,7 @@ class Cache : public BaseCache * @return A new Packet containing the request, or NULL if the * current request in cpu_pkt should just be forwarded on. */ - PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk, + PacketPtr getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk, bool needsExclusive) const; /** @@ -362,6 +370,12 @@ class Cache : public BaseCache */ MSHR *getNextMSHR(); + /** + * Send up a snoop request and find cached copies. If cached copies are + * found, set the BLOCK_CACHED flag in pkt. + */ + bool isCachedAbove(const PacketPtr pkt) const; + /** * Selects an outstanding request to service. Called when the * cache gets granted the downstream bus in timing mode. @@ -370,12 +384,13 @@ class Cache : public BaseCache PacketPtr getTimingPacket(); /** - * Marks a request as in service (sent on the bus). This can have side - * effect since storage for no response commands is deallocated once they - * are successfully sent. - * @param pkt The request that was sent on the bus. + * Marks a request as in service (sent on the bus). This can have + * side effect since storage for no response commands is + * deallocated once they are successfully sent. Also remember if + * we are expecting a dirty response from another cache, + * effectively making this MSHR the ordering point. */ - void markInService(MSHR *mshr, PacketPtr pkt = 0); + void markInService(MSHR *mshr, bool pending_dirty_resp); /** * Return whether there are any outstanding misses. @@ -418,4 +433,62 @@ class Cache : public BaseCache void unserialize(Checkpoint *cp, const std::string §ion); }; +/** + * Wrap a method and present it as a cache block visitor. + * + * For example the forEachBlk method in the tag arrays expects a + * callable object/function as their parameter. This class wraps a + * method in an object and presents callable object that adheres to + * the cache block visitor protocol. + */ +class CacheBlkVisitorWrapper : public CacheBlkVisitor +{ + public: + typedef bool (Cache::*VisitorPtr)(CacheBlk &blk); + + CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor) + : cache(_cache), visitor(_visitor) {} + + bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE { + return (cache.*visitor)(blk); + } + + private: + Cache &cache; + VisitorPtr visitor; +}; + +/** + * Cache block visitor that determines if there are dirty blocks in a + * cache. + * + * Use with the forEachBlk method in the tag array to determine if the + * array contains dirty blocks. + */ +class CacheBlkIsDirtyVisitor : public CacheBlkVisitor +{ + public: + CacheBlkIsDirtyVisitor() + : _isDirty(false) {} + + bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE { + if (blk.isDirty()) { + _isDirty = true; + return false; + } else { + return true; + } + } + + /** + * Does the array contain a dirty line? + * + * \return true if yes, false otherwise. + */ + bool isDirty() const { return _isDirty; }; + + private: + bool _isDirty; +}; + #endif // __CACHE_HH__