X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmem%2Fcache%2Fcache.hh;h=4c70d3a4040436812c05af586b602663249d0e87;hb=a262908acc0a641700a03fcea89c48133f0467cd;hp=e14b2efe87835dc0ffb2f434b018a2b5d5eaa319;hpb=a9b7c558fd6c00dacbdf36f4617c03a19c198b08;p=gem5.git diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index e14b2efe8..4c70d3a40 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2012-2014 ARM Limited + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2002-2005 The Regents of The University of Michigan * All rights reserved. * @@ -29,6 +41,7 @@ * Dave Greene * Steve Reinhardt * Ron Dreslinski + * Andreas Hansson */ /** @@ -39,432 +52,443 @@ #ifndef __CACHE_HH__ #define __CACHE_HH__ -#include "base/compression/base.hh" #include "base/misc.hh" // fatal, panic, and warn -#include "cpu/smt.hh" // SMT_MAX_THREADS - -#include "mem/cache/base_cache.hh" -#include "mem/cache/cache_blk.hh" -#include "mem/cache/miss/miss_buffer.hh" - +#include "mem/cache/base.hh" +#include "mem/cache/blk.hh" +#include "mem/cache/mshr.hh" +#include "mem/cache/tags/base.hh" #include "sim/eventq.hh" //Forward decleration -class MSHR; class BasePrefetcher; /** * A template-policy based cache. The behavior of the cache can be altered by * supplying different template policies. TagStore handles all tag and data - * storage @sa TagStore. Buffering handles all misses and writes/writebacks - * @sa MissQueue. Coherence handles all coherence policy details @sa - * UniCoherence, SimpleMultiCoherence. + * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System" */ -template class Cache : public BaseCache { public: - /** Define the type of cache block to use. */ - typedef typename TagStore::BlkType BlkType; - /** A typedef for a list of BlkType pointers. */ - typedef typename TagStore::BlkList BlkList; - bool prefetchAccess; + /** A typedef for a list of CacheBlk pointers. */ + typedef std::list BlkList; protected: - class CpuSidePort : public CachePort + /** + * The CPU-side port extends the base cache slave port with access + * functions for functional, atomic and timing requests. + */ + class CpuSidePort : public CacheSlavePort { - public: - CpuSidePort(const std::string &_name, - Cache *_cache); - - // BaseCache::CachePort just has a BaseCache *; this function - // lets us get back the type info we lost when we stored the - // cache pointer there. - Cache *myCache() { - return static_cast *>(cache); - } + private: - void processRequestEvent(); - void processResponseEvent(); + // a pointer to our specific cache implementation + Cache *cache; - virtual void getDeviceAddressRanges(AddrRangeList &resp, - bool &snoop); + protected: - virtual bool recvTiming(PacketPtr pkt); + virtual bool recvTimingSnoopResp(PacketPtr pkt); - virtual void recvRetry(); + virtual bool recvTimingReq(PacketPtr pkt); virtual Tick recvAtomic(PacketPtr pkt); virtual void recvFunctional(PacketPtr pkt); - typedef EventWrapper - ResponseEvent; + virtual AddrRangeList getAddrRanges() const; - typedef EventWrapper - RequestEvent; + public: + + CpuSidePort(const std::string &_name, Cache *_cache, + const std::string &_label); - virtual void scheduleRequestEvent(Tick t) { - new RequestEvent(this, t); - } }; - class MemSidePort : public CachePort + /** + * Override the default behaviour of sendDeferredPacket to enable + * the memory-side cache port to also send requests based on the + * current MSHR status. This queue has a pointer to our specific + * cache implementation and is used by the MemSidePort. + */ + class CacheReqPacketQueue : public ReqPacketQueue { + + protected: + + Cache &cache; + SnoopRespPacketQueue &snoopRespQueue; + public: - MemSidePort(const std::string &_name, - Cache *_cache); - - // BaseCache::CachePort just has a BaseCache *; this function - // lets us get back the type info we lost when we stored the - // cache pointer there. - Cache *myCache() { - return static_cast *>(cache); - } - void processRequestEvent(); - void processResponseEvent(); + CacheReqPacketQueue(Cache &cache, MasterPort &port, + SnoopRespPacketQueue &snoop_resp_queue, + const std::string &label) : + ReqPacketQueue(cache, port, label), cache(cache), + snoopRespQueue(snoop_resp_queue) { } + + /** + * Override the normal sendDeferredPacket and do not only + * consider the transmit list (used for responses), but also + * requests. + */ + virtual void sendDeferredPacket(); - virtual void getDeviceAddressRanges(AddrRangeList &resp, - bool &snoop); + }; - virtual bool recvTiming(PacketPtr pkt); + /** + * The memory-side port extends the base cache master port with + * access functions for functional, atomic and timing snoops. + */ + class MemSidePort : public CacheMasterPort + { + private: - virtual void recvRetry(); + /** The cache-specific queue. */ + CacheReqPacketQueue _reqQueue; - virtual Tick recvAtomic(PacketPtr pkt); + SnoopRespPacketQueue _snoopRespQueue; - virtual void recvFunctional(PacketPtr pkt); + // a pointer to our specific cache implementation + Cache *cache; - typedef EventWrapper - ResponseEvent; + protected: - typedef EventWrapper - RequestEvent; + virtual void recvTimingSnoopReq(PacketPtr pkt); - virtual void scheduleRequestEvent(Tick t) { - new RequestEvent(this, t); - } + virtual bool recvTimingResp(PacketPtr pkt); + + virtual Tick recvAtomicSnoop(PacketPtr pkt); + + virtual void recvFunctionalSnoop(PacketPtr pkt); + + public: + + MemSidePort(const std::string &_name, Cache *_cache, + const std::string &_label); }; /** Tag and data Storage */ - TagStore *tags; - /** Miss and Writeback handler */ - MissBuffer *missQueue; - /** Coherence protocol. */ - Coherence *coherence; + BaseTags *tags; /** Prefetcher */ BasePrefetcher *prefetcher; - /** - * The clock ratio of the outgoing bus. - * Used for calculating critical word first. - */ - int busRatio; - - /** - * The bus width in bytes of the outgoing bus. - * Used for calculating critical word first. - */ - int busWidth; + /** Temporary cache block for occasional transitory use */ + CacheBlk *tempBlock; /** - * The latency of a hit in this device. + * This cache should allocate a block on a line-sized write miss. */ - int hitLatency; - - /** - * A permanent mem req to always be used to cause invalidations. - * Used to append to target list, to cause an invalidation. - */ - PacketPtr invalidatePkt; - Request *invalidateReq; + const bool doFastWrites; /** - * Policy class for performing compression. + * Turn line-sized writes into WriteInvalidate transactions. */ - CompressionAlgorithm *compressionAlg; + void promoteWholeLineWrites(PacketPtr pkt); /** - * The block size of this cache. Set to value in the Tags object. + * Notify the prefetcher on every access, not just misses. */ - const int16_t blkSize; + const bool prefetchOnAccess; /** - * Can this cache should allocate a block on a line-sized write miss. + * @todo this is a temporary workaround until the 4-phase code is committed. + * upstream caches need this packet until true is returned, so hold it for + * deletion until a subsequent call */ - const bool doFastWrites; - - const bool prefetchMiss; + std::vector pendingDelete; /** - * Can the data can be stored in a compressed form. + * Does all the processing necessary to perform the provided request. + * @param pkt The memory request to perform. + * @param blk The cache block to be updated. + * @param lat The latency of the access. + * @param writebacks List for any writebacks that need to be performed. + * @return Boolean indicating whether the request was satisfied. */ - const bool storeCompressed; + bool access(PacketPtr pkt, CacheBlk *&blk, + Cycles &lat, PacketList &writebacks); /** - * Do we need to compress blocks on writebacks (i.e. because - * writeback bus is compressed but storage is not)? + *Handle doing the Compare and Swap function for SPARC. */ - const bool compressOnWriteback; + void cmpAndSwap(CacheBlk *blk, PacketPtr pkt); /** - * The latency of a compression operation. + * Find a block frame for new block at address addr targeting the + * given security space, assuming that the block is not currently + * in the cache. Append writebacks if any to provided packet + * list. Return free block frame. May return NULL if there are + * no replaceable blocks at the moment. */ - const int16_t compLatency; + CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks); /** - * Should we use an adaptive compression scheme. + * Populates a cache block and handles all outstanding requests for the + * satisfied fill request. This version takes two memory requests. One + * contains the fill data, the other is an optional target to satisfy. + * @param pkt The memory request with the fill data. + * @param blk The cache block if it already exists. + * @param writebacks List for any writebacks that need to be performed. + * @return Pointer to the new cache block. */ - const bool adaptiveCompression; + CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk, + PacketList &writebacks); - /** - * Do writebacks need to be compressed (i.e. because writeback bus - * is compressed), whether or not they're already compressed for - * storage. - */ - const bool writebackCompressed; /** - * Compare the internal block data to the fast access block data. - * @param blk The cache block to check. - * @return True if the data is the same. + * Performs the access specified by the request. + * @param pkt The request to perform. + * @return The result of the access. */ - bool verifyData(BlkType *blk); + bool recvTimingReq(PacketPtr pkt); /** - * Update the internal data of the block. The data to write is assumed to - * be in the fast access data. - * @param blk The block with the data to update. - * @param writebacks A list to store any generated writebacks. - * @param compress_block True if we should compress this block + * Insert writebacks into the write buffer */ - void updateData(BlkType *blk, PacketList &writebacks, bool compress_block); + void doWritebacks(PacketList& writebacks, Tick forward_time); /** - * Handle a replacement for the given request. - * @param blk A pointer to the block, usually NULL - * @param pkt The memory request to satisfy. - * @param new_state The new state of the block. - * @param writebacks A list to store any generated writebacks. + * Handles a response (cache line fill/write ack) from the bus. + * @param pkt The response packet */ - BlkType* doReplacement(BlkType *blk, PacketPtr &pkt, - CacheBlk::State new_state, PacketList &writebacks); + void recvTimingResp(PacketPtr pkt); /** - * Does all the processing necessary to perform the provided request. - * @param pkt The memory request to perform. - * @param lat The latency of the access. - * @param writebacks List for any writebacks that need to be performed. - * @param update True if the replacement data should be updated. - * @return Pointer to the cache block touched by the request. NULL if it - * was a miss. + * Snoops bus transactions to maintain coherence. + * @param pkt The current bus transaction. */ - BlkType* handleAccess(PacketPtr &pkt, int & lat, - PacketList & writebacks, bool update = true); - + void recvTimingSnoopReq(PacketPtr pkt); /** - *Handle doing the Compare and Swap function for SPARC. + * Handle a snoop response. + * @param pkt Snoop response packet */ - void cmpAndSwap(BlkType *blk, PacketPtr &pkt); + void recvTimingSnoopResp(PacketPtr pkt); /** - * Populates a cache block and handles all outstanding requests for the - * satisfied fill request. This version takes an MSHR pointer and uses its - * request to fill the cache block, while repsonding to its targets. - * @param blk The cache block if it already exists. - * @param mshr The MSHR that contains the fill data and targets to satisfy. - * @param new_state The state of the new cache block. - * @param writebacks List for any writebacks that need to be performed. - * @return Pointer to the new cache block. + * Performs the access specified by the request. + * @param pkt The request to perform. + * @return The number of ticks required for the access. */ - BlkType* handleFill(BlkType *blk, MSHR * mshr, CacheBlk::State new_state, - PacketList & writebacks, PacketPtr pkt); + Tick recvAtomic(PacketPtr pkt); /** - * Populates a cache block and handles all outstanding requests for the - * satisfied fill request. This version takes two memory requests. One - * contains the fill data, the other is an optional target to satisfy. - * Used for Cache::probe. - * @param blk The cache block if it already exists. - * @param pkt The memory request with the fill data. - * @param new_state The state of the new cache block. - * @param writebacks List for any writebacks that need to be performed. - * @param target The memory request to perform after the fill. - * @return Pointer to the new cache block. + * Snoop for the provided request in the cache and return the estimated + * time taken. + * @param pkt The memory request to snoop + * @return The number of ticks required for the snoop. */ - BlkType* handleFill(BlkType *blk, PacketPtr &pkt, - CacheBlk::State new_state, - PacketList & writebacks, PacketPtr target = NULL); + Tick recvAtomicSnoop(PacketPtr pkt); /** - * Sets the blk to the new state and handles the given request. - * @param blk The cache block being snooped. - * @param new_state The new coherence state for the block. - * @param pkt The request to satisfy + * Performs the access specified by the request. + * @param pkt The request to perform. + * @param fromCpuSide from the CPU side port or the memory side port */ - void handleSnoop(BlkType *blk, CacheBlk::State new_state, - PacketPtr &pkt); + void functionalAccess(PacketPtr pkt, bool fromCpuSide); + + void satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk, + bool deferred_response = false, + bool pending_downgrade = false); + bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, CacheBlk *blk); + + void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, + bool already_copied, bool pending_inval); /** * Sets the blk to the new state. * @param blk The cache block being snooped. * @param new_state The new coherence state for the block. */ - void handleSnoop(BlkType *blk, CacheBlk::State new_state); + void handleSnoop(PacketPtr ptk, CacheBlk *blk, + bool is_timing, bool is_deferred, bool pending_inval); /** * Create a writeback request for the given block. * @param blk The block to writeback. * @return The writeback request for the block. */ - PacketPtr writebackBlk(BlkType *blk); - - public: + PacketPtr writebackBlk(CacheBlk *blk); - class Params - { - public: - TagStore *tags; - MissBuffer *missQueue; - Coherence *coherence; - BaseCache::Params baseParams; - BasePrefetcher*prefetcher; - bool prefetchAccess; - int hitLatency; - CompressionAlgorithm *compressionAlg; - const int16_t blkSize; - const bool doFastWrites; - const bool prefetchMiss; - const bool storeCompressed; - const bool compressOnWriteback; - const int16_t compLatency; - const bool adaptiveCompression; - const bool writebackCompressed; - - Params(TagStore *_tags, MissBuffer *mq, Coherence *coh, - BaseCache::Params params, - BasePrefetcher *_prefetcher, - bool prefetch_access, int hit_latency, - bool do_fast_writes, - bool store_compressed, bool adaptive_compression, - bool writeback_compressed, - CompressionAlgorithm *_compressionAlg, int comp_latency, - bool prefetch_miss) - : tags(_tags), missQueue(mq), coherence(coh), - baseParams(params), - prefetcher(_prefetcher), prefetchAccess(prefetch_access), - hitLatency(hit_latency), - compressionAlg(_compressionAlg), - blkSize(_tags->getBlockSize()), - doFastWrites(do_fast_writes), - prefetchMiss(prefetch_miss), - storeCompressed(store_compressed), - compressOnWriteback(!store_compressed && writeback_compressed), - compLatency(comp_latency), - adaptiveCompression(adaptive_compression), - writebackCompressed(writeback_compressed) - { - } - }; - - /** Instantiates a basic cache object. */ - Cache(const std::string &_name, Params ¶ms); + /** + * Create a CleanEvict request for the given block. + * @param blk The block to evict. + * @return The CleanEvict request for the block. + */ + PacketPtr cleanEvictBlk(CacheBlk *blk); - virtual Port *getPort(const std::string &if_name, int idx = -1); - virtual void deletePortRefs(Port *p); - void regStats(); + void memWriteback(); + void memInvalidate(); + bool isDirty() const; /** - * Performs the access specified by the request. - * @param pkt The request to perform. - * @return The result of the access. + * Cache block visitor that writes back dirty cache blocks using + * functional writes. + * + * \return Always returns true. + */ + bool writebackVisitor(CacheBlk &blk); + /** + * Cache block visitor that invalidates all blocks in the cache. + * + * @warn Dirty cache lines will not be written back to memory. + * + * \return Always returns true. */ - bool access(PacketPtr &pkt); + bool invalidateVisitor(CacheBlk &blk); /** - * Selects a request to send on the bus. - * @return The memory request to service. + * Squash all requests associated with specified thread. + * intended for use by I-cache. + * @param threadNum The thread to squash. */ - PacketPtr getPacket(); + void squash(int threadNum); /** - * Was the request was sent successfully? - * @param pkt The request. - * @param success True if the request was sent successfully. + * Generate an appropriate downstream bus request packet for the + * given parameters. + * @param cpu_pkt The upstream request that needs to be satisfied. + * @param blk The block currently in the cache corresponding to + * cpu_pkt (NULL if none). + * @param needsExclusive Indicates that an exclusive copy is required + * even if the request in cpu_pkt doesn't indicate that. + * @return A new Packet containing the request, or NULL if the + * current request in cpu_pkt should just be forwarded on. */ - void sendResult(PacketPtr &pkt, MSHR* mshr, bool success); + PacketPtr getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk, + bool needsExclusive) const; /** - * Handles a response (cache line fill/write ack) from the bus. - * @param pkt The request being responded to. + * Return the next MSHR to service, either a pending miss from the + * mshrQueue, a buffered write from the write buffer, or something + * from the prefetcher. This function is responsible for + * prioritizing among those sources on the fly. */ - void handleResponse(PacketPtr &pkt); + MSHR *getNextMSHR(); /** - * Snoops bus transactions to maintain coherence. - * @param pkt The current bus transaction. + * Send up a snoop request and find cached copies. If cached copies are + * found, set the BLOCK_CACHED flag in pkt. */ - void snoop(PacketPtr &pkt); + bool isCachedAbove(const PacketPtr pkt) const; - void snoopResponse(PacketPtr &pkt); + /** + * Selects an outstanding request to service. Called when the + * cache gets granted the downstream bus in timing mode. + * @return The request to service, NULL if none found. + */ + PacketPtr getTimingPacket(); /** - * Squash all requests associated with specified thread. - * intended for use by I-cache. - * @param threadNum The thread to squash. + * Marks a request as in service (sent on the bus). This can have + * side effect since storage for no response commands is + * deallocated once they are successfully sent. Also remember if + * we are expecting a dirty response from another cache, + * effectively making this MSHR the ordering point. */ - void squash(int threadNum) - { - missQueue->squash(threadNum); - } + void markInService(MSHR *mshr, bool pending_dirty_resp); /** - * Return the number of outstanding misses in a Cache. - * Default returns 0. - * - * @retval unsigned The number of missing still outstanding. + * Return whether there are any outstanding misses. */ - unsigned outstandingMisses() const + bool outstandingMisses() const { - return missQueue->getMisses(); + return mshrQueue.allocated != 0; + } + + CacheBlk *findBlock(Addr addr, bool is_secure) const { + return tags->findBlock(addr, is_secure); + } + + bool inCache(Addr addr, bool is_secure) const { + return (tags->findBlock(addr, is_secure) != 0); + } + + bool inMissQueue(Addr addr, bool is_secure) const { + return (mshrQueue.findMatch(addr, is_secure) != 0); } /** - * Perform the access specified in the request and return the estimated - * time of completion. This function can either update the hierarchy state - * or just perform the access wherever the data is found depending on the - * state of the update flag. - * @param pkt The memory request to satisfy - * @param update If true, update the hierarchy, otherwise just perform the - * request. - * @return The estimated completion time. + * Find next request ready time from among possible sources. */ - Tick probe(PacketPtr &pkt, bool update, CachePort * otherSidePort); + Tick nextMSHRReadyTime() const; - /** - * Snoop for the provided request in the cache and return the estimated - * time of completion. - * @todo Can a snoop probe not change state? - * @param pkt The memory request to satisfy - * @param update If true, update the hierarchy, otherwise just perform the - * request. - * @return The estimated completion time. + public: + /** Instantiates a basic cache object. */ + Cache(const Params *p); + + /** Non-default destructor is needed to deallocate memory. */ + virtual ~Cache(); + + void regStats(); + + /** serialize the state of the caches + * We currently don't support checkpointing cache state, so this panics. */ - Tick snoopProbe(PacketPtr &pkt); + virtual void serialize(std::ostream &os); + void unserialize(Checkpoint *cp, const std::string §ion); +}; + +/** + * Wrap a method and present it as a cache block visitor. + * + * For example the forEachBlk method in the tag arrays expects a + * callable object/function as their parameter. This class wraps a + * method in an object and presents callable object that adheres to + * the cache block visitor protocol. + */ +class CacheBlkVisitorWrapper : public CacheBlkVisitor +{ + public: + typedef bool (Cache::*VisitorPtr)(CacheBlk &blk); - bool inCache(Addr addr) { - return (tags->findBlock(addr) != 0); + CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor) + : cache(_cache), visitor(_visitor) {} + + bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE { + return (cache.*visitor)(blk); } - bool inMissQueue(Addr addr) { - return (missQueue->findMSHR(addr) != 0); + private: + Cache &cache; + VisitorPtr visitor; +}; + +/** + * Cache block visitor that determines if there are dirty blocks in a + * cache. + * + * Use with the forEachBlk method in the tag array to determine if the + * array contains dirty blocks. + */ +class CacheBlkIsDirtyVisitor : public CacheBlkVisitor +{ + public: + CacheBlkIsDirtyVisitor() + : _isDirty(false) {} + + bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE { + if (blk.isDirty()) { + _isDirty = true; + return false; + } else { + return true; + } } + + /** + * Does the array contain a dirty line? + * + * \return true if yes, false otherwise. + */ + bool isDirty() const { return _isDirty; }; + + private: + bool _isDirty; }; #endif // __CACHE_HH__