X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmem%2Fcache%2Fcache_blk.hh;h=dce0ce434570ad9f5cfc1c8b54736e4cf7433204;hb=b8a4a911eed17315320a6948d369f791617adfeb;hp=02fdd7a5143a20179514f7521a5d17633e9a814a;hpb=fc281d0b64fca8d2809ec462148acb7cf0461ea5;p=gem5.git diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/cache_blk.hh index 02fdd7a51..dce0ce434 100644 --- a/src/mem/cache/cache_blk.hh +++ b/src/mem/cache/cache_blk.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2012-2018 ARM Limited + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2003-2005 The Regents of The University of Michigan * All rights reserved. * @@ -26,45 +38,58 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Erik Hallnor + * Andreas Sandberg */ /** @file * Definitions of a simple cache block class. */ -#ifndef __CACHE_BLK_HH__ -#define __CACHE_BLK_HH__ +#ifndef __MEM_CACHE_CACHE_BLK_HH__ +#define __MEM_CACHE_CACHE_BLK_HH__ + +#include +#include +#include +#include +#include -#include "sim/root.hh" // for Tick -#include "arch/isa_traits.hh" // for Addr +#include "base/printable.hh" +#include "base/types.hh" +#include "mem/cache/replacement_policies/base.hh" +#include "mem/packet.hh" +#include "mem/request.hh" /** * Cache block status bit assignments */ -enum CacheBlkStatusBits { +enum CacheBlkStatusBits : unsigned { /** valid, readable */ - BlkValid = 0x01, + BlkValid = 0x01, /** write permission */ - BlkWritable = 0x02, + BlkWritable = 0x02, + /** read permission (yes, block can be valid but not readable) */ + BlkReadable = 0x04, /** dirty (modified) */ - BlkDirty = 0x04, - /** compressed */ - BlkCompressed = 0x08, - /** block was referenced */ - BlkReferenced = 0x10, + BlkDirty = 0x08, /** block was a hardware prefetch yet unaccessed*/ - BlkHWPrefetched = 0x20 + BlkHWPrefetched = 0x20, + /** block holds data from the secure memory space */ + BlkSecure = 0x40, + /** block holds compressed data */ + BlkCompressed = 0x80 }; /** * A Basic Cache block. * Contains the tag, status, and a pointer to data. */ -class CacheBlk +class CacheBlk : public ReplaceableEntry { public: - /** The address space ID of this block. */ - int asid; + /** Task Id associated with this block */ + uint32_t task_id; + /** Data block tag value. */ Addr tag; /** @@ -75,8 +100,6 @@ class CacheBlk * referenced by this block. */ uint8_t *data; - /** the number of bytes stored in this block. */ - int size; /** block state: OR of CacheBlkStatusBit */ typedef unsigned State; @@ -84,54 +107,100 @@ class CacheBlk /** The current status of this block. @sa CacheBlockStatusBits */ State status; - /** Which curTick will this block be accessable */ - Tick whenReady; - /** - * The set this block belongs to. - * @todo Move this into subclasses when we fix CacheTags to use them. + * Which curTick() will this block be accessible. Its value is only + * meaningful if the block is valid. */ - int set; + Tick whenReady; /** Number of references to this block since it was brought in. */ - int refCount; + unsigned refCount; + + /** holds the source requestor ID for this block. */ + int srcMasterId; - CacheBlk() - : asid(-1), tag(0), data(0) ,size(0), status(0), whenReady(0), xc(0), - set(-1), refCount(0) - {} + /** + * Tick on which the block was inserted in the cache. Its value is only + * meaningful if the block is valid. + */ + Tick tickInserted; + protected: /** - * Copy the state of the given block into this one. - * @param rhs The block to copy. - * @return a const reference to this block. + * Represents that the indicated thread context has a "lock" on + * the block, in the LL/SC sense. */ - const CacheBlk& operator=(const CacheBlk& rhs) + class Lock { + public: + ContextID contextId; // locking context + Addr lowAddr; // low address of lock range + Addr highAddr; // high address of lock range + + // check for matching execution context, and an address that + // is within the lock + bool matches(const RequestPtr &req) const + { + Addr req_low = req->getPaddr(); + Addr req_high = req_low + req->getSize() -1; + return (contextId == req->contextId()) && + (req_low >= lowAddr) && (req_high <= highAddr); + } + + // check if a request is intersecting and thus invalidating the lock + bool intersects(const RequestPtr &req) const + { + Addr req_low = req->getPaddr(); + Addr req_high = req_low + req->getSize() - 1; + + return (req_low <= highAddr) && (req_high >= lowAddr); + } + + Lock(const RequestPtr &req) + : contextId(req->contextId()), + lowAddr(req->getPaddr()), + highAddr(lowAddr + req->getSize() - 1) + { + } + }; + + /** List of thread contexts that have performed a load-locked (LL) + * on the block since the last store. */ + std::list lockList; + + public: + CacheBlk() : data(nullptr), tickInserted(0) { - asid = rhs.asid; - tag = rhs.tag; - data = rhs.data; - size = rhs.size; - status = rhs.status; - whenReady = rhs.whenReady; - xc = rhs.xc; - set = rhs.set; - refCount = rhs.refCount; - return *this; + invalidate(); } + CacheBlk(const CacheBlk&) = delete; + CacheBlk& operator=(const CacheBlk&) = delete; + virtual ~CacheBlk() {}; + /** * Checks the write permissions of this block. * @return True if the block is writable. */ bool isWritable() const { - const int needed_bits = BlkWritable | BlkValid; + const State needed_bits = BlkWritable | BlkValid; + return (status & needed_bits) == needed_bits; + } + + /** + * Checks the read permissions of this block. Note that a block + * can be valid but not readable if there is an outstanding write + * upgrade miss. + * @return True if the block is readable. + */ + bool isReadable() const + { + const State needed_bits = BlkReadable | BlkValid; return (status & needed_bits) == needed_bits; } /** - * Checks that a block is valid (readable). + * Checks that a block is valid. * @return True if the block is valid. */ bool isValid() const @@ -139,61 +208,311 @@ class CacheBlk return (status & BlkValid) != 0; } + /** + * Invalidate the block and clear all state. + */ + virtual void invalidate() + { + tag = MaxAddr; + task_id = ContextSwitchTaskId::Unknown; + status = 0; + whenReady = MaxTick; + refCount = 0; + srcMasterId = Request::invldMasterId; + lockList.clear(); + } + /** * Check to see if a block has been written. * @return True if the block is dirty. */ - bool isModified() const + bool isDirty() const { return (status & BlkDirty) != 0; } /** - * Check to see if this block contains compressed data. - * @return True iF the block's data is compressed. + * Check if this block was the result of a hardware prefetch, yet to + * be touched. + * @return True if the block was a hardware prefetch, unaccesed. */ - bool isCompressed() const + bool wasPrefetched() const { - return (status & BlkCompressed) != 0; + return (status & BlkHWPrefetched) != 0; } /** - * Check if this block has been referenced. - * @return True if the block has been referenced. + * Check if this block holds data from the secure memory space. + * @return True if the block holds data from the secure memory space. */ - bool isReferenced() const + bool isSecure() const { - return (status & BlkReferenced) != 0; + return (status & BlkSecure) != 0; } /** - * Check if this block was the result of a hardware prefetch, yet to - * be touched. - * @return True if the block was a hardware prefetch, unaccesed. + * Set valid bit. */ - bool isPrefetch() const + virtual void setValid() { - return (status & BlkHWPrefetched) != 0; + assert(!isValid()); + status |= BlkValid; + } + + /** + * Set secure bit. + */ + virtual void setSecure() + { + status |= BlkSecure; + } + + /** + * Get tick at which block's data will be available for access. + * + * @return Data ready tick. + */ + Tick getWhenReady() const + { + assert(whenReady != MaxTick); + return whenReady; + } + + /** + * Set tick at which block's data will be available for access. The new + * tick must be chronologically sequential with respect to previous + * accesses. + * + * @param tick New data ready tick. + */ + void setWhenReady(const Tick tick) + { + assert(tick >= tickInserted); + whenReady = tick; } + /** + * Set member variables when a block insertion occurs. Resets reference + * count to 1 (the insertion counts as a reference), and touch block if + * it hadn't been touched previously. Sets the insertion tick to the + * current tick. Marks the block valid. + * + * @param tag Block address tag. + * @param is_secure Whether the block is in secure space or not. + * @param src_master_ID The source requestor ID. + * @param task_ID The new task ID. + */ + virtual void insert(const Addr tag, const bool is_secure, + const int src_master_ID, const uint32_t task_ID); + /** + * Track the fact that a local locked was issued to the + * block. Invalidate any previous LL to the same address. + */ + void trackLoadLocked(PacketPtr pkt) + { + assert(pkt->isLLSC()); + auto l = lockList.begin(); + while (l != lockList.end()) { + if (l->intersects(pkt->req)) + l = lockList.erase(l); + else + ++l; + } + + lockList.emplace_front(pkt->req); + } + + /** + * Clear the any load lock that intersect the request, and is from + * a different context. + */ + void clearLoadLocks(const RequestPtr &req) + { + auto l = lockList.begin(); + while (l != lockList.end()) { + if (l->intersects(req) && l->contextId != req->contextId()) { + l = lockList.erase(l); + } else { + ++l; + } + } + } + + /** + * Pretty-print tag, set and way, and interpret state bits to readable form + * including mapping to a MOESI state. + * + * @return string with basic state information + */ + virtual std::string print() const + { + /** + * state M O E S I + * writable 1 0 1 0 0 + * dirty 1 1 0 0 0 + * valid 1 1 1 1 0 + * + * state writable dirty valid + * M 1 1 1 + * O 0 1 1 + * E 1 0 1 + * S 0 0 1 + * I 0 0 0 + * + * Note that only one cache ever has a block in Modified or + * Owned state, i.e., only one cache owns the block, or + * equivalently has the BlkDirty bit set. However, multiple + * caches on the same path to memory can have a block in the + * Exclusive state (despite the name). Exclusive means this + * cache has the only copy at this level of the hierarchy, + * i.e., there may be copies in caches above this cache (in + * various states), but there are no peers that have copies on + * this branch of the hierarchy, and no caches at or above + * this level on any other branch have copies either. + **/ + unsigned state = isWritable() << 2 | isDirty() << 1 | isValid(); + char s = '?'; + switch (state) { + case 0b111: s = 'M'; break; + case 0b011: s = 'O'; break; + case 0b101: s = 'E'; break; + case 0b001: s = 'S'; break; + case 0b000: s = 'I'; break; + default: s = 'T'; break; // @TODO add other types + } + return csprintf("state: %x (%c) valid: %d writable: %d readable: %d " + "dirty: %d | tag: %#x set: %#x way: %#x", status, s, + isValid(), isWritable(), isReadable(), isDirty(), tag, + getSet(), getWay()); + } + + /** + * Handle interaction of load-locked operations and stores. + * @return True if write should proceed, false otherwise. Returns + * false only in the case of a failed store conditional. + */ + bool checkWrite(PacketPtr pkt) + { + assert(pkt->isWrite()); + + // common case + if (!pkt->isLLSC() && lockList.empty()) + return true; + + const RequestPtr &req = pkt->req; + + if (pkt->isLLSC()) { + // it's a store conditional... have to check for matching + // load locked. + bool success = false; + + auto l = lockList.begin(); + while (!success && l != lockList.end()) { + if (l->matches(pkt->req)) { + // it's a store conditional, and as far as the + // memory system can tell, the requesting + // context's lock is still valid. + success = true; + lockList.erase(l); + } else { + ++l; + } + } + + req->setExtraData(success ? 1 : 0); + // clear any intersected locks from other contexts (our LL + // should already have cleared them) + clearLoadLocks(req); + return success; + } else { + // a normal write, if there is any lock not from this + // context we clear the list, thus for a private cache we + // never clear locks on normal writes + clearLoadLocks(req); + return true; + } + } }; /** - * Output a CacheBlk to the given ostream. - * @param out The stream for the output. - * @param blk The cache block to print. - * - * @return The output stream. + * Special instance of CacheBlk for use with tempBlk that deals with its + * block address regeneration. + * @sa Cache */ -inline std::ostream & -operator<<(std::ostream &out, const CacheBlk &blk) +class TempCacheBlk final : public CacheBlk { - out << std::hex << std::endl; - out << " Tag: " << blk.tag << std::endl; - out << " Status: " << blk.status << std::endl; + private: + /** + * Copy of the block's address, used to regenerate tempBlock's address. + */ + Addr _addr; - return(out << std::dec); -} + public: + /** + * Creates a temporary cache block, with its own storage. + * @param size The size (in bytes) of this cache block. + */ + TempCacheBlk(unsigned size) : CacheBlk() + { + data = new uint8_t[size]; + } + TempCacheBlk(const TempCacheBlk&) = delete; + TempCacheBlk& operator=(const TempCacheBlk&) = delete; + ~TempCacheBlk() { delete [] data; }; + + /** + * Invalidate the block and clear all state. + */ + void invalidate() override { + CacheBlk::invalidate(); + + _addr = MaxAddr; + } + + void insert(const Addr addr, const bool is_secure, + const int src_master_ID=0, const uint32_t task_ID=0) override + { + // Make sure that the block has been properly invalidated + assert(status == 0); + + // Set block address + _addr = addr; + + // Set secure state + if (is_secure) { + setSecure(); + } + + // Validate block + setValid(); + } + + /** + * Get block's address. + * + * @return addr Address value. + */ + Addr getAddr() const + { + return _addr; + } +}; + +/** + * Simple class to provide virtual print() method on cache blocks + * without allocating a vtable pointer for every single cache block. + * Just wrap the CacheBlk object in an instance of this before passing + * to a function that requires a Printable object. + */ +class CacheBlkPrintWrapper : public Printable +{ + CacheBlk *blk; + public: + CacheBlkPrintWrapper(CacheBlk *_blk) : blk(_blk) {} + virtual ~CacheBlkPrintWrapper() {} + void print(std::ostream &o, int verbosity = 0, + const std::string &prefix = "") const; +}; -#endif //__CACHE_BLK_HH__ +#endif //__MEM_CACHE_CACHE_BLK_HH__