X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmem%2Fcache%2Fprefetch%2FPrefetcher.py;h=c7ddcda1c2d1bcdcbe2c790d9ed0428da65d0aee;hb=2cb1449ede402e3ad242ae97ee959a41683e8ca3;hp=36e25415114fdda7e7b7a9d67218ce6914750182;hpb=53cbc6b9e3b90e5ca902a7da17b5d35f73f8f5d4;p=gem5.git diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py index 36e254151..c7ddcda1c 100644 --- a/src/mem/cache/prefetch/Prefetcher.py +++ b/src/mem/cache/prefetch/Prefetcher.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012, 2014 ARM Limited +# Copyright (c) 2012, 2014, 2019 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -65,6 +65,7 @@ class BasePrefetcher(ClockedObject): cxx_header = "mem/cache/prefetch/base.hh" cxx_exports = [ PyBindMethod("addEventProbe"), + PyBindMethod("addTLB"), ] sys = Param.System(Parent.any, "System this prefetcher belongs to") @@ -88,6 +89,8 @@ class BasePrefetcher(ClockedObject): # Override the normal SimObject::regProbeListeners method and # register deferred event handlers. def regProbeListeners(self): + for tlb in self._tlbs: + self.getCCObject().addTLB(tlb.getCCObject()) for event in self._events: event.register() self.getCCObject().regProbeListeners() @@ -98,6 +101,18 @@ class BasePrefetcher(ClockedObject): if len(probeNames) <= 0: raise TypeError("probeNames must have at least one element") self.addEvent(HWPProbeEvent(self, simObj, *probeNames)) + _tlbs = [] + def registerTLB(self, simObj): + if not isinstance(simObj, SimObject): + raise TypeError("argument must be a SimObject type") + self._tlbs.append(simObj) + +class MultiPrefetcher(BasePrefetcher): + type = 'MultiPrefetcher' + cxx_class = 'MultiPrefetcher' + cxx_header = 'mem/cache/prefetch/multi.hh' + + prefetchers = VectorParam.BasePrefetcher([], "Array of prefetchers") class QueuedPrefetcher(BasePrefetcher): type = "QueuedPrefetcher" @@ -106,12 +121,26 @@ class QueuedPrefetcher(BasePrefetcher): cxx_header = "mem/cache/prefetch/queued.hh" latency = Param.Int(1, "Latency for generated prefetches") queue_size = Param.Int(32, "Maximum number of queued prefetches") + max_prefetch_requests_with_pending_translation = Param.Int(32, + "Maximum number of queued prefetches that have a missing translation") queue_squash = Param.Bool(True, "Squash queued prefetch on demand access") queue_filter = Param.Bool(True, "Don't queue redundant prefetches") cache_snoop = Param.Bool(False, "Snoop cache to eliminate redundant request") tag_prefetch = Param.Bool(True, "Tag prefetch with PC of generating access") + # The throttle_control_percentage controls how many of the candidate + # addresses generated by the prefetcher will be finally turned into + # prefetch requests + # - If set to 100, all candidates can be discarded (one request + # will always be allowed to be generated) + # - Setting it to 0 will disable the throttle control, so requests are + # created for all candidates + # - If set to 60, 40% of candidates will generate a request, and the + # remaining 60% will be generated depending on the current accuracy + throttle_control_percentage = Param.Percent(0, "Percentage of requests \ + that can be throttled depending on the accuracy of the prefetcher.") + class StridePrefetcher(QueuedPrefetcher): type = 'StridePrefetcher' cxx_class = 'StridePrefetcher' @@ -142,6 +171,41 @@ class TaggedPrefetcher(QueuedPrefetcher): degree = Param.Int(2, "Number of prefetches to generate") +class IndirectMemoryPrefetcher(QueuedPrefetcher): + type = 'IndirectMemoryPrefetcher' + cxx_class = 'IndirectMemoryPrefetcher' + cxx_header = "mem/cache/prefetch/indirect_memory.hh" + pt_table_entries = Param.MemorySize("16", + "Number of entries of the Prefetch Table") + pt_table_assoc = Param.Unsigned(16, "Associativity of the Prefetch Table") + pt_table_indexing_policy = Param.BaseIndexingPolicy( + SetAssociative(entry_size = 1, assoc = Parent.pt_table_assoc, + size = Parent.pt_table_entries), + "Indexing policy of the pattern table") + pt_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(), + "Replacement policy of the pattern table") + max_prefetch_distance = Param.Unsigned(16, "Maximum prefetch distance") + num_indirect_counter_bits = Param.Unsigned(3, + "Number of bits of the indirect counter") + ipd_table_entries = Param.MemorySize("4", + "Number of entries of the Indirect Pattern Detector") + ipd_table_assoc = Param.Unsigned(4, + "Associativity of the Indirect Pattern Detector") + ipd_table_indexing_policy = Param.BaseIndexingPolicy( + SetAssociative(entry_size = 1, assoc = Parent.ipd_table_assoc, + size = Parent.ipd_table_entries), + "Indexing policy of the Indirect Pattern Detector") + ipd_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(), + "Replacement policy of the Indirect Pattern Detector") + shift_values = VectorParam.Int([2, 3, 4, -3], "Shift values to evaluate") + addr_array_len = Param.Unsigned(4, "Number of misses tracked") + prefetch_threshold = Param.Unsigned(2, + "Counter threshold to start the indirect prefetching") + stream_counter_threshold = Param.Unsigned(4, + "Counter threshold to enable the stream prefetcher") + streaming_distance = Param.Unsigned(4, + "Number of prefetches to generate when using the stream prefetcher") + class SignaturePathPrefetcher(QueuedPrefetcher): type = 'SignaturePathPrefetcher' cxx_class = 'SignaturePathPrefetcher' @@ -162,7 +226,8 @@ class SignaturePathPrefetcher(QueuedPrefetcher): signature_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(), "Replacement policy of the signature table") - max_counter_value = Param.UInt8(7, "Maximum pattern counter value") + num_counter_bits = Param.UInt8(3, + "Number of bits of the saturating counters") pattern_table_entries = Param.MemorySize("4096", "Number of entries of the pattern table") pattern_table_assoc = Param.Unsigned(1, @@ -190,7 +255,7 @@ class SignaturePathPrefetcherV2(SignaturePathPrefetcher): signature_table_assoc = 1 pattern_table_entries = "512" pattern_table_assoc = 1 - max_counter_value = 15 + num_counter_bits = 4 prefetch_confidence_threshold = 0.25 lookahead_confidence_threshold = 0.25 @@ -283,8 +348,8 @@ class IrregularStreamBufferPrefetcher(QueuedPrefetcher): cxx_class = "IrregularStreamBufferPrefetcher" cxx_header = "mem/cache/prefetch/irregular_stream_buffer.hh" - max_counter_value = Param.Unsigned(3, - "Maximum value of the confidence counter") + num_counter_bits = Param.Unsigned(2, + "Number of bits of the confidence counter") chunk_size = Param.Unsigned(256, "Maximum number of addresses in a temporal stream") degree = Param.Unsigned(4, "Number of prefetches to generate") @@ -341,3 +406,110 @@ class SlimAMPMPrefetcher(QueuedPrefetcher): dcpt = Param.DeltaCorrelatingPredictionTables( SlimDeltaCorrelatingPredictionTables(), "Delta Correlating Prediction Tables object") + +class BOPPrefetcher(QueuedPrefetcher): + type = "BOPPrefetcher" + cxx_class = "BOPPrefetcher" + cxx_header = "mem/cache/prefetch/bop.hh" + score_max = Param.Unsigned(31, "Max. score to update the best offset") + round_max = Param.Unsigned(100, "Max. round to update the best offset") + bad_score = Param.Unsigned(10, "Score at which the HWP is disabled") + rr_size = Param.Unsigned(64, "Number of entries of each RR bank") + tag_bits = Param.Unsigned(12, "Bits used to store the tag") + offset_list_size = Param.Unsigned(46, + "Number of entries in the offsets list") + negative_offsets_enable = Param.Bool(True, + "Initialize the offsets list also with negative values \ + (i.e. the table will have half of the entries with positive \ + offsets and the other half with negative ones)") + delay_queue_enable = Param.Bool(True, "Enable the delay queue") + delay_queue_size = Param.Unsigned(15, + "Number of entries in the delay queue") + delay_queue_cycles = Param.Cycles(60, + "Cycles to delay a write in the left RR table from the delay \ + queue") + +class SBOOEPrefetcher(QueuedPrefetcher): + type = 'SBOOEPrefetcher' + cxx_class = 'SBOOEPrefetcher' + cxx_header = "mem/cache/prefetch/sbooe.hh" + latency_buffer_size = Param.Int(32, "Entries in the latency buffer") + sequential_prefetchers = Param.Int(9, "Number of sequential prefetchers") + sandbox_entries = Param.Int(1024, "Size of the address buffer") + score_threshold_pct = Param.Percent(25, "Min. threshold to issue a \ + prefetch. The value is the percentage of sandbox entries to use") + +class STeMSPrefetcher(QueuedPrefetcher): + type = "STeMSPrefetcher" + cxx_class = "STeMSPrefetcher" + cxx_header = "mem/cache/prefetch/spatio_temporal_memory_streaming.hh" + + spatial_region_size = Param.MemorySize("2kB", + "Memory covered by a hot zone") + active_generation_table_entries = Param.MemorySize("64", + "Number of entries in the active generation table") + active_generation_table_assoc = Param.Unsigned(64, + "Associativity of the active generation table") + active_generation_table_indexing_policy = Param.BaseIndexingPolicy( + SetAssociative(entry_size = 1, + assoc = Parent.active_generation_table_assoc, + size = Parent.active_generation_table_entries), + "Indexing policy of the active generation table") + active_generation_table_replacement_policy = Param.BaseReplacementPolicy( + LRURP(), "Replacement policy of the active generation table") + + pattern_sequence_table_entries = Param.MemorySize("16384", + "Number of entries in the pattern sequence table") + pattern_sequence_table_assoc = Param.Unsigned(16384, + "Associativity of the pattern sequence table") + pattern_sequence_table_indexing_policy = Param.BaseIndexingPolicy( + SetAssociative(entry_size = 1, + assoc = Parent.pattern_sequence_table_assoc, + size = Parent.pattern_sequence_table_entries), + "Indexing policy of the pattern sequence table") + pattern_sequence_table_replacement_policy = Param.BaseReplacementPolicy( + LRURP(), "Replacement policy of the pattern sequence table") + + region_miss_order_buffer_entries = Param.Unsigned(131072, + "Number of entries of the Region Miss Order Buffer") + reconstruction_entries = Param.Unsigned(256, + "Number of reconstruction entries") + +class HWPProbeEventRetiredInsts(HWPProbeEvent): + def register(self): + if self.obj: + for name in self.names: + self.prefetcher.getCCObject().addEventProbeRetiredInsts( + self.obj.getCCObject(), name) + +class PIFPrefetcher(QueuedPrefetcher): + type = 'PIFPrefetcher' + cxx_class = 'PIFPrefetcher' + cxx_header = "mem/cache/prefetch/pif.hh" + cxx_exports = [ + PyBindMethod("addEventProbeRetiredInsts"), + ] + + prec_spatial_region_bits = Param.Unsigned(2, + "Number of preceding addresses in the spatial region") + succ_spatial_region_bits = Param.Unsigned(8, + "Number of subsequent addresses in the spatial region") + compactor_entries = Param.Unsigned(2, "Entries in the temp. compactor") + stream_address_buffer_entries = Param.Unsigned(7, "Entries in the SAB") + history_buffer_size = Param.Unsigned(16, "Entries in the history buffer") + + index_entries = Param.MemorySize("64", + "Number of entries in the index") + index_assoc = Param.Unsigned(64, + "Associativity of the index") + index_indexing_policy = Param.BaseIndexingPolicy( + SetAssociative(entry_size = 1, assoc = Parent.index_assoc, + size = Parent.index_entries), + "Indexing policy of the index") + index_replacement_policy = Param.BaseReplacementPolicy(LRURP(), + "Replacement policy of the index") + + def listenFromProbeRetiredInstructions(self, simObj): + if not isinstance(simObj, SimObject): + raise TypeError("argument must be of SimObject type") + self.addEvent(HWPProbeEventRetiredInsts(self, simObj,"RetiredInstsPC"))