X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmem%2Fcache%2Fprefetch%2FPrefetcher.py;h=c7ddcda1c2d1bcdcbe2c790d9ed0428da65d0aee;hb=2cb1449ede402e3ad242ae97ee959a41683e8ca3;hp=aaa140887a725be0756886f0ef73eb295c157f63;hpb=5caa4517345d4833af44e510f78717ee7e0ad8d4;p=gem5.git

diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py
index aaa140887..c7ddcda1c 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012, 2014 ARM Limited
+# Copyright (c) 2012, 2014, 2019 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -65,6 +65,7 @@ class BasePrefetcher(ClockedObject):
     cxx_header = "mem/cache/prefetch/base.hh"
     cxx_exports = [
         PyBindMethod("addEventProbe"),
+        PyBindMethod("addTLB"),
     ]
     sys = Param.System(Parent.any, "System this prefetcher belongs to")
 
@@ -88,6 +89,8 @@ class BasePrefetcher(ClockedObject):
     # Override the normal SimObject::regProbeListeners method and
     # register deferred event handlers.
     def regProbeListeners(self):
+        for tlb in self._tlbs:
+            self.getCCObject().addTLB(tlb.getCCObject())
         for event in self._events:
            event.register()
         self.getCCObject().regProbeListeners()
@@ -98,6 +101,18 @@ class BasePrefetcher(ClockedObject):
         if len(probeNames) <= 0:
             raise TypeError("probeNames must have at least one element")
         self.addEvent(HWPProbeEvent(self, simObj, *probeNames))
+    _tlbs = []
+    def registerTLB(self, simObj):
+        if not isinstance(simObj, SimObject):
+            raise TypeError("argument must be a SimObject type")
+        self._tlbs.append(simObj)
+
+class MultiPrefetcher(BasePrefetcher):
+    type = 'MultiPrefetcher'
+    cxx_class = 'MultiPrefetcher'
+    cxx_header = 'mem/cache/prefetch/multi.hh'
+
+    prefetchers = VectorParam.BasePrefetcher([], "Array of prefetchers")
 
 class QueuedPrefetcher(BasePrefetcher):
     type = "QueuedPrefetcher"
@@ -106,12 +121,26 @@ class QueuedPrefetcher(BasePrefetcher):
     cxx_header = "mem/cache/prefetch/queued.hh"
     latency = Param.Int(1, "Latency for generated prefetches")
     queue_size = Param.Int(32, "Maximum number of queued prefetches")
+    max_prefetch_requests_with_pending_translation = Param.Int(32,
+        "Maximum number of queued prefetches that have a missing translation")
     queue_squash = Param.Bool(True, "Squash queued prefetch on demand access")
     queue_filter = Param.Bool(True, "Don't queue redundant prefetches")
     cache_snoop = Param.Bool(False, "Snoop cache to eliminate redundant request")
 
     tag_prefetch = Param.Bool(True, "Tag prefetch with PC of generating access")
 
+    # The throttle_control_percentage controls how many of the candidate
+    # addresses generated by the prefetcher will be finally turned into
+    # prefetch requests
+    # - If set to 100, all candidates can be discarded (one request
+    #   will always be allowed to be generated)
+    # - Setting it to 0 will disable the throttle control, so requests are
+    #   created for all candidates
+    # - If set to 60, 40% of candidates will generate a request, and the
+    #   remaining 60% will be generated depending on the current accuracy
+    throttle_control_percentage = Param.Percent(0, "Percentage of requests \
+        that can be throttled depending on the accuracy of the prefetcher.")
+
 class StridePrefetcher(QueuedPrefetcher):
     type = 'StridePrefetcher'
     cxx_class = 'StridePrefetcher'
@@ -156,8 +185,8 @@ class IndirectMemoryPrefetcher(QueuedPrefetcher):
     pt_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
         "Replacement policy of the pattern table")
     max_prefetch_distance = Param.Unsigned(16, "Maximum prefetch distance")
-    max_indirect_counter_value = Param.Unsigned(8,
-        "Maximum value of the indirect counter")
+    num_indirect_counter_bits = Param.Unsigned(3,
+        "Number of bits of the indirect counter")
     ipd_table_entries = Param.MemorySize("4",
         "Number of entries of the Indirect Pattern Detector")
     ipd_table_assoc = Param.Unsigned(4,
@@ -197,7 +226,8 @@ class SignaturePathPrefetcher(QueuedPrefetcher):
     signature_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
         "Replacement policy of the signature table")
 
-    max_counter_value = Param.UInt8(7, "Maximum pattern counter value")
+    num_counter_bits = Param.UInt8(3,
+        "Number of bits of the saturating counters")
     pattern_table_entries = Param.MemorySize("4096",
         "Number of entries of the pattern table")
     pattern_table_assoc = Param.Unsigned(1,
@@ -225,7 +255,7 @@ class SignaturePathPrefetcherV2(SignaturePathPrefetcher):
     signature_table_assoc = 1
     pattern_table_entries = "512"
     pattern_table_assoc = 1
-    max_counter_value = 15
+    num_counter_bits = 4
     prefetch_confidence_threshold = 0.25
     lookahead_confidence_threshold = 0.25
 
@@ -318,8 +348,8 @@ class IrregularStreamBufferPrefetcher(QueuedPrefetcher):
     cxx_class = "IrregularStreamBufferPrefetcher"
     cxx_header = "mem/cache/prefetch/irregular_stream_buffer.hh"
 
-    max_counter_value = Param.Unsigned(3,
-        "Maximum value of the confidence counter")
+    num_counter_bits = Param.Unsigned(2,
+        "Number of bits of the confidence counter")
     chunk_size = Param.Unsigned(256,
         "Maximum number of addresses in a temporal stream")
     degree = Param.Unsigned(4, "Number of prefetches to generate")